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公开(公告)号：US20240355620A1
公开(公告)日：2024-10-24
申请号：US18713455
申请日：2022-10-25
IPC分类号： H01L21/02 , H01L29/20 , H01L29/786
CPC分类号： H01L21/02389 , H01L21/0242 , H01L21/0262 , H01L29/2003 , H01L29/7869
摘要： A nitride semiconductor substrate includes: a silicon single-crystal substrate; and a nitride semiconductor thin film formed on the silicon single-crystal substrate, wherein the silicon single-crystal substrate has a carbon concentration of 5E16 atoms/cm3 or more and 2E17 atoms/cm3 or less. This provides a nitride semiconductor substrate resistant against plastic deformation and a manufacturing method therefor.
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公开(公告)号：US20240297224A1
公开(公告)日：2024-09-05
申请号：US18272621
申请日：2022-01-17
IPC分类号： H01L29/20 , H01L21/02 , H01L29/205
CPC分类号： H01L29/2003 , H01L21/0254 , H01L29/205
摘要： A nitride semiconductor substrate, including a Ga-containing nitride semiconductor thin film formed on a substrate for film-forming in which a single crystal silicon layer is formed on a composite substrate in which a plurality of layers is bonded, wherein the nitride semiconductor substrate has a region where the Ga-containing nitride semiconductor thin film is not formed inward from an edge of the single crystal silicon layer being a growth surface of the nitride semiconductor thin film. This provides: a nitride semiconductor substrate with inhibited generation of a reaction mark; and a manufacturing method therefor.
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3.发明公开公开(公告)号：US20240258462A1
公开(公告)日：2024-08-01
申请号：US18565663
申请日：2022-06-27
CPC分类号： H01L33/32 , H01L33/0075 , H01L33/06
摘要： An epitaxial wafer for an ultraviolet ray emission device including: a first supporting substrate being transparent for ultraviolet ray and having heat resistance; a seed crystal layer of an AlxGa1-xN (0.5
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公开(公告)号：US20240165765A1
公开(公告)日：2024-05-23
申请号：US18283051
申请日：2022-03-03
发明人： Ryo HASEGAWA
CPC分类号： B24B9/065 , B24B7/228 , H01L21/02021
摘要： A method for manufacturing a semiconductor wafer, including: a chamfering step of grinding at least a periphery of a wafer to form a chamfered portion having a wafer edge portion and a wafer notch portion; a double-side polishing step; a mirror-surface chamfering step; and a mirror polishing step, wherein the mirror-surface chamfering step includes: a first mirror-surface chamfering process of polishing the wafer notch portion in the chamfered portion before the double-side polishing step; and a second mirror-surface chamfering process of polishing the wafer notch portion and the wafer edge portion after the double-side polishing step, and a polishing rate of the wafer notch portion in the second mirror-surface chamfering process is smaller than a polishing rate of the wafer notch portion in the first mirror-surface chamfering process.
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公开(公告)号：US20240142390A1
公开(公告)日：2024-05-02
申请号：US18280825
申请日：2022-02-25
发明人： Yutaka SHIGA , Toru TAKAHASHI , Hisao MURAKI
CPC分类号： G01N21/9505 , C30B29/36 , C30B33/10 , H01L22/12
摘要： A method for evaluating crystal defects in a silicon carbide single crystal wafer, the method including steps of: etching a silicon carbide single crystal wafer with melted KOH so that a size of an etch pit due to a threading edge dislocation is 10 to 50 μm; obtaining microscopic images by automatic photographing at a plurality of positions on a surface of the silicon carbide single crystal wafer after the etching; determining presence or absence of a defect dense part in each of all the obtained microscopic images based on a continued length of the etch pit formed by the etching; and classifying all the obtained microscopic images into microscopic images having the defect dense part and microscopic images not having the defect dense part to evaluate a dense state of crystal defects in the silicon carbide single crystal wafer.
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公开(公告)号：US11928178B2
公开(公告)日：2024-03-12
申请号：US17268326
申请日：2019-08-01
发明人： Masato Ohnishi
摘要： A wafer is prepared, and a thickness shape of the prepared wafer at each position in a radial direction is measured for each of a predetermined number of angles into which 360 degrees of a circumference around the center of the wafer are divided. The thickness shape obtained by a measuring machine for each angle is approximated with a sixth or higher order polynomial, and a function of the wafer thickness at the position in the radial direction is created. The thickness shape outputted by the measuring machine and a thickness shape outputted by the function are compared with each other, and an error on the entire surface of the wafer is confirmed to be not greater than a predetermined error. After the confirmation, information of the function for each angle is attached to the wafer as data representing the wafer shape and supplied to a user.
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公开(公告)号：US20240003046A1
公开(公告)日：2024-01-04
申请号：US18037802
申请日：2021-11-01
摘要： A single crystal manufacturing including: main chamber; pulling chamber; thermal shield member provided so as to face a silicon melt; rectifying cylinder provided on the thermal shield member so as to enclose the silicon single crystal being pulled up; cooling cylinder provided so as to encircle the silicon single crystal being pulled up and including an extending portion extending toward the silicon melt; and cooling auxiliary cylinder fitted to inside of the cooling cylinder. The extending portion of the cooling cylinder includes a bottom surface facing the silicon melt. The cooling auxiliary cylinder includes at least a first portion surrounding the bottom surface of the cooling cylinder and a second portion surrounding an upper end portion of the rectifying cylinder. This enables provision of the apparatus capable of manufacturing a single crystal with a carbon concentration lower than that according to the conventional technologies.
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公开(公告)号：US11806827B2
公开(公告)日：2023-11-07
申请号：US16086554
申请日：2017-02-24
发明人： Yoshihiro Usami
CPC分类号： B24B27/0633 , B24B5/363 , B24B5/37 , B24B27/06 , B28D5/04 , B28D5/045 , H01L21/304 , B65H54/28 , B65H59/10 , B65H2701/36
摘要： A method for manufacturing a wire saw apparatus including a wire supply reel; a long roller; wire guides; a wire winding reel; and a tension arm controlled to move within a control angle of ±A (°) set in advance and configured to apply tension to the wire, the method including the steps of: measuring a surface roughness Rmax of the long roller; measuring an angle a (°) of the tension arm at which the tension arm swings outside a range of the control angle set in advance while the wire is extending from the wire supply reel; calculating R1×2×A÷(|a|+A)=R2, where R1 (μm) represents the measured surface roughness Rmax of the long roller; and adjusting the surface roughness Rmax of the long roller to the calculated numerical value R2 or less. The method for manufacturing a wire saw apparatus can prevent the tension arm from greatly swinging outside the control range.
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公开(公告)号：US20230276716A1
公开(公告)日：2023-08-31
申请号：US18014221
申请日：2021-05-26
发明人： Tsuyoshi OHTSUKI , Hiroshi TAKENO
IPC分类号： H10N60/01
CPC分类号： H10N60/0884 , H01P3/003
摘要： A method produces a semiconductor apparatus for a quantum computer. The apparatus includes: a semiconductor substrate; a quantum computer device formed on the semiconductor substrate; and a peripheral circuit formed on the semiconductor substrate and connected to the quantum computer device. The apparatus is to be used as a quantum computer. The method includes: a step of forming the quantum computer device and the peripheral circuit on the semiconductor substrate; and a step of deactivating a carrier in the semiconductor substrate by irradiation of a particle beam to at least a formation part for the quantum computer device and a formation part for the peripheral circuit in the semiconductor substrate. The method for producing a semiconductor apparatus for a quantum computer can produce a semiconductor apparatus for a quantum computer having excellent 3HD characteristics.
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公开(公告)号：US20230268222A1
公开(公告)日：2023-08-24
申请号：US18024194
申请日：2021-07-27
发明人： Isao YOKOKAWA
IPC分类号： H01L21/762 , C23C16/40 , C23C16/56
CPC分类号： H01L21/76251 , C23C16/401 , C23C16/56
摘要： A method for manufacturing an SOI wafer including: a step of forming a silicon oxide film by thermal oxidation on an entire surface of a base wafer containing a dopant; and bonding a main surface of a bond wafer to a first main surface via the silicon oxide film, wherein, prior to the thermal oxidation step, a step of forming a CVD insulator film on a second main surface; and a step of forming, on the first main surface, a barrier silicon layer containing a dopant at a lower concentration than a dopant concentration of the base wafer, and in the thermal oxidation step, the barrier silicon layer is thermally oxidized to produce a barrier silicon oxide film, and in the bonding step, the bond wafer is bonded to the base wafer via the barrier silicon oxide film as a part of the silicon oxide film.
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