公开(公告)号：US20080093116A1

公开(公告)日：2008-04-24

申请号：US11856490

申请日：2007-09-17

Applicant: Pao-Nan Lee ,  Sung-Mao Wu

Inventor： Pao-Nan Lee ,  Sung-Mao Wu

IPC: H05K1/11

CPC classification number: H05K1/0245 ,  H01L2223/6638 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09645

Abstract: A semiconductor substrate for transmitting a differential pair is provided. The semiconductor substrate includes a substrate body and at least one via. The via has an opening on a surface layer of the substrate body and includes a first conductive element, a second conductive element and a ground element therein. The first conductive element, the second conductive element and the ground element are electrically isolated to one another. The ground element is electrically connected to a ground layer of the substrate body. The first conductive element and the second conductive element pass through the ground layer of the substrate body and are electrically isolated with the ground layer of the substrate body. The first conductive element is used for transmitting a positive differential signal and the second conductive element is used for transmitting a negative differential signal.

Abstract translation: 提供用于传输差分对的半导体衬底。 半导体衬底包括衬底主体和至少一个通孔。 通孔在基板主体的表面层上具有开口，并且在其中包括第一导电元件，第二导电元件和接地元件。 第一导电元件，第二导电元件和接地元件彼此电隔离。 接地元件电连接到衬底主体的接地层。 第一导电元件和第二导电元件穿过衬底主体的接地层并与衬底主体的接地层电隔离。 第一导电元件用于发送正差分信号，第二导电元件用于发送负差分信号。

公开(公告)号：US20070205499A1

公开(公告)日：2007-09-06

申请号：US11645598

申请日：2006-12-27

Applicant: Wei-Chung Wang ,  Sung-Mao Wu ,  Hsueh-An Yang ,  Kuo-Pin Yang ,  Chian-Chi Lin

Inventor： Wei-Chung Wang ,  Sung-Mao Wu ,  Hsueh-An Yang ,  Kuo-Pin Yang ,  Chian-Chi Lin

IPC: H01L23/12

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H04R1/02 ,  H04R1/04 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.

Abstract translation: 本发明涉及一种微机电麦克风包装系统。 微电机麦克风包装系统包括基片，芯片，微电机麦克风，导电胶，非导电胶和盖。 衬底具有第一表面。 芯片安装在基板的第一表面上。 微机电麦克风安装在基板的第一表面上，并与芯片电连接。 芯片由非导电胶水封闭。 导电胶被导电胶包围。 盖安装在基板的第一表面上以形成容纳空间，并具有声孔。 微机电麦克风包装系统利用封装芯片和非导电胶的导电胶来屏蔽外部噪声的干扰并获得屏蔽效果。 此外，盖子不需要由金属材料制成。

公开(公告)号：US20060108690A1

公开(公告)日：2006-05-25

申请号：US11183824

申请日：2005-07-19

Applicant: Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

Inventor： Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

IPC: H01L23/48

CPC classification number: H05K1/0216 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/09054 ,  H05K2201/09309 ,  H01L2924/00

Abstract: A circuit board with reduced simultaneous switching noise. The circuit board comprises a first conductor plane with a first fixed potential, a dielectric layer, at least a build-up via and a second conductor plane with a second fixed potential. The dielectric layer is formed on the first conductor plane. The build-up vias are formed in the dielectric layer and filled with a conductive material. The second conductor plane is in contact with the conductive material in the build-up vias. The depth of the build-up vias is less than one fourth of a signal wavelength.

Abstract translation: 具有降低同时开关噪声的电路板。 电路板包括具有第一固定电位的第一导体平面，介电层，至少具有第二固定电位的积聚通孔和第二导体平面。 电介质层形成在第一导体平面上。 积聚通孔形成在电介质层中并填充有导电材料。 第二导体平面与积层通孔中的导电材料接触。 积聚通孔的深度小于信号波长的四分之一。

公开(公告)号：US20060081960A1

公开(公告)日：2006-04-20

申请号：US11183864

申请日：2005-07-19

Applicant: Sung-Mao Wu

Inventor： Sung-Mao Wu

IPC: H01L29/00

CPC classification number: H01G4/35 ,  H01G4/33 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0231 ,  H05K1/0253 ,  H05K1/162 ,  H05K2201/09318 ,  H05K2201/09736 ,  H01L2924/00

Abstract: An integrated capacitor on a packaging substrate. The integrated capacitor comprises a conductor plane, a first dielectric layer and a signal transmission layer. The conductor plane has an extrusion layer of a first thickness. The first extrusion layer and the conductor plane are made of the same material. The first dielectric layer is formed on the conductor plane. The signal transmission layer is formed on the first dielectric layer.

Abstract translation: 封装基板上的集成电容器。 集成电容器包括导体平面，第一介电层和信号传输层。 导体平面具有第一厚度的挤出层。 第一挤出层和导体平面由相同的材料制成。 第一电介质层形成在导体平面上。 信号传输层形成在第一电介质层上。

公开(公告)号：US20050046046A1

公开(公告)日：2005-03-03

申请号：US10962564

申请日：2004-10-13

Applicant: Chi-Tsung Chiu ,  Su Tao ,  Sung-Mao Wu

Inventor： Chi-Tsung Chiu ,  Su Tao ,  Sung-Mao Wu

IPC: H01L21/58 ,  H01L23/29 ,  H01L23/31 ,  H01L23/49 ,  H01L23/552 ,  H01L21/48 ,  H01L23/28

CPC classification number: H01L23/29 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2223/6611 ,  H01L2223/6622 ,  H01L2224/45144 ,  H01L2224/45572 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/83 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a plurality of wires, and a molding compound. In this case, the semiconductor die is attached to the substrate. Each of the wires respectively has a center conductive layer, a dielectric layer, and a metal layer. Each of the center conductive layers connects the semiconductor die to the substrate. Each of the dielectric layers covers each of the center conductive layers, and the metal layers cover the dielectric layers. The molding compound encapsulates the semiconductor die and the wires. This invention also provides another semiconductor package structure, including a substrate, a semiconductor die, a plurality of wires, and a conductive molding compound. Each of the wires respectively has a center conductive layer and a dielectric layer. The conductive molding compound is made of a conductive material. Furthermore, the invention also provides a method for manufacturing the semiconductor package structure.

Abstract translation: 半导体封装结构包括衬底，半导体管芯，多根电线和模塑料。 在这种情况下，将半导体管芯附接到基板。 各导线分别具有中心导电层，电介质层和金属层。 每个中心导电层将半导体管芯连接到衬底。 每个电介质层覆盖每个中心导电层，并且金属层覆盖电介质层。 模制化合物封装半导体管芯和电线。 本发明还提供了另一种半导体封装结构，其包括基片，半导体片，多根丝和导电模塑料。 每根导线分别具有中心导电层和电介质层。 导电模塑料由导电材料制成。 此外，本发明还提供了一种用于制造半导体封装结构的方法。

公开(公告)号：US07248134B2

公开(公告)日：2007-07-24

申请号：US11186859

申请日：2005-07-22

Applicant: Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

Inventor： Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

IPC: H01P3/08

CPC classification number: H05K1/0216 ,  H01G4/236 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09509

Abstract: An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.

Abstract translation: 用积层通孔实现的电感和电容器。 电感器和电容器包括导体平面，电介质层，电感器/电容器，用于引导积聚通孔和导体层。 在电感器/电容器中存在导电材料，其导致积聚通孔，并且其第一端与导体平面接触。 感应电感通孔的电感长度大于信号波长的四分之一，而导体积聚通孔的导体长度小于信号波长的四分之一。

公开(公告)号：US07084639B2

公开(公告)日：2006-08-01

申请号：US10667513

申请日：2003-09-23

Applicant: Sung Mao Wu ,  Chi Tsung Chiu

Inventor： Sung Mao Wu ,  Chi Tsung Chiu

IPC: G01R35/00 ,  G01D18/00

CPC classification number: G01R35/005

Abstract: An impedance standard substrate for calibrating a vector network analyzer includes a first surface and a second surface opposite to the first surface. A thru-circuit has two contacts electrically connected to each other. The two contacts are disposed on the first surface and the second surface, respectively. The impedance standard substrate further includes a pair of open-circuits, a pair of short-circuits, and a pair of load-circuits disposed on the first surface and the second surface, respectively.

Abstract translation: 用于校准矢量网络分析仪的阻抗标准基板包括与第一表面相对的第一表面和第二表面。 通路具有彼此电连接的两个触点。 两个触点分别设置在第一表面和第二表面上。 阻抗标准基板还包括分别设置在第一表面和第二表面上的一对开路，一对短路和一对负载电路。

公开(公告)号：US07945062B2

公开(公告)日：2011-05-17

申请号：US11645598

申请日：2006-12-27

Applicant: Wei-Chung Wang ,  Sung-Mao Wu ,  Hsueh-An Yang ,  Kuo-Pin Yang ,  Chian-Chi Lin

Inventor： Wei-Chung Wang ,  Sung-Mao Wu ,  Hsueh-An Yang ,  Kuo-Pin Yang ,  Chian-Chi Lin

IPC: H04R25/00 ,  H04R9/08 ,  H04R11/04 ,  H04R17/02 ,  H04R19/04 ,  H04R21/02 ,  H01L23/02 ,  H01L23/28

CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H04R1/02 ,  H04R1/04 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.

Abstract translation: 本发明涉及一种微机电麦克风包装系统。 微电机麦克风包装系统包括基片，芯片，微电机麦克风，导电胶，非导电胶和盖。 衬底具有第一表面。 芯片安装在基板的第一表面上。 微机电麦克风安装在基板的第一表面上，并与芯片电连接。 芯片由非导电胶水封闭。 导电胶被导电胶包围。 盖安装在基板的第一表面上以形成容纳空间，并具有声孔。 微机电麦克风包装系统利用封装芯片和非导电胶的导电胶来屏蔽外部噪声的干扰并获得屏蔽效果。 此外，盖子不需要由金属材料制成。

公开(公告)号：US20100265009A1

公开(公告)日：2010-10-21

申请号：US12425045

申请日：2009-04-16

Applicant: Tzyy-Sheng Horng ,  Chien-Hsun Chen ,  Chien-Hsiang Huang ,  Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

Inventor： Tzyy-Sheng Horng ,  Chien-Hsun Chen ,  Chien-Hsiang Huang ,  Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

IPC: H03H7/01 ,  H03H7/12

CPC classification number: H03H7/0115 ,  H03H2001/0085

Abstract: A stacked LC resonator includes a parallel-plate capacitor, a dielectric layer and a spiral inductor. The parallel-plate capacitor has a first metal layer, a second metal layer opposed to the first metal layer and a middle dielectric layer formed between the first and second metal layers. The dielectric layer is formed on the second metal layer of the parallel-plate capacitor. The spiral inductor is formed on the dielectric layer and electrically connected with the first and second metal layers of the parallel-plate capacitor.

Abstract translation: 叠层LC谐振器包括平行板电容器，电介质层和螺旋电感器。 平行板电容器具有第一金属层，与第一金属层相对的第二金属层和形成在第一和第二金属层之间的中间介电层。 电介质层形成在平行板电容器的第二金属层上。 螺旋电感器形成在电介质层上并与平行板电容器的第一和第二金属层电连接。

公开(公告)号：US20060103483A1

公开(公告)日：2006-05-18

申请号：US11186859

申请日：2005-07-22

Applicant: Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

Inventor： Sung-Mao Wu ,  Chi-Tsung Chiu ,  Chih-Pin Hung

IPC: H03H5/02

CPC classification number: H05K1/0216 ,  H01G4/236 ,  H05K1/025 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09509

Abstract: An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.

Abstract translation: 用积层通孔实现的电感和电容器。 电感器和电容器包括导体平面，电介质层，电感器/电容器，用于引导积聚通孔和导体层。 在电感器/电容器中存在导电材料，其导致积聚通孔，并且其第一端与导体平面接触。 感应电感通孔的电感长度大于信号波长的四分之一，而导体积聚通孔的导体长度小于信号波长的四分之一。