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公开(公告)号:US07939916B2
公开(公告)日:2011-05-10
申请号:US11627041
申请日:2007-01-25
申请人: Alan O'Donnell , Oliver Kierse , Thomas M. Goida
发明人: Alan O'Donnell , Oliver Kierse , Thomas M. Goida
IPC分类号: H01L23/552
CPC分类号: H01L23/3128 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/566 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/3142 , H01L23/3171 , H01L23/3178 , H01L23/3185 , H01L2224/13022 , H01L2224/73203 , H01L2224/94 , H01L2924/00011 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10158 , H01L2224/0401 , H01L2224/03
摘要: An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.
摘要翻译: 电子封装包括包含电子电路并具有顶表面和底表面的晶片管芯衬底。 顶部保护层基本上比基板薄,并且覆盖顶部表面。 底部保护层基本上比衬底更薄并且覆盖底部表面。 电路触点围绕底部保护层分布,用于将衬底电子电路电耦合到外部电子电路。
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公开(公告)号:US20080179730A1
公开(公告)日:2008-07-31
申请号:US11627041
申请日:2007-01-25
申请人: Alan O'Donnell , Oliver Kierse , Thomas M. Goida
发明人: Alan O'Donnell , Oliver Kierse , Thomas M. Goida
CPC分类号: H01L23/3128 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/566 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L23/3142 , H01L23/3171 , H01L23/3178 , H01L23/3185 , H01L2224/13022 , H01L2224/73203 , H01L2224/94 , H01L2924/00011 , H01L2924/00014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/10158 , H01L2224/0401 , H01L2224/03
摘要: An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.
摘要翻译: 电子封装包括包含电子电路并具有顶表面和底表面的晶片管芯衬底。 顶部保护层基本上比基板薄,并且覆盖顶部表面。 底部保护层基本上比衬底更薄并且覆盖底部表面。 电路触点围绕底部保护层分布,用于将衬底电子电路电耦合到外部电子电路。
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公开(公告)号:US08026599B2
公开(公告)日:2011-09-27
申请号:US11517131
申请日:2006-09-07
申请人: Alan O'Donnell
发明人: Alan O'Donnell
CPC分类号: H01L23/552 , H01L21/56 , H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favor of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.
摘要翻译: 本申请涉及晶片级芯片尺寸封装(WLCSP)的制造,这是一种CSP型,其中传统的引线键合装置被省去,有利于通过导电凸块(通常是焊球)直接接触到 集成电路。 WLCSPs与细间距球栅阵列(BGA)和基于引线框架的芯片尺寸封装(CSP)不同,因为大多数封装工艺步骤在晶圆级执行。 提供了一种封装和制造方法,其通过在WLCSP封装的不活动侧提供基本上不透明的涂层并且至少部分地在WLCSP封装的侧面上来防止光进入WLCSP封装的内部电路。
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公开(公告)号:US20080064137A1
公开(公告)日:2008-03-13
申请号:US11517131
申请日:2006-09-07
申请人: Alan O'Donnell
发明人: Alan O'Donnell
IPC分类号: H01L21/00
CPC分类号: H01L23/552 , H01L21/56 , H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favour of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.
摘要翻译: 本申请涉及晶片级芯片尺寸封装(WLCSP)的制造,这是一种CSP型,其中传统的引线键合装置被省去,有利于通过导电凸块(通常是焊球)直接接触到 集成电路。 WLCSPs与细间距球栅阵列(BGA)和基于引线框架的芯片尺寸封装(CSP)不同,因为大多数封装工艺步骤在晶圆级执行。 提供了一种封装和制造方法,其通过在WLCSP封装的不活动侧提供基本上不透明的涂层并且至少部分地在WLCSP封装的侧面上来防止光进入WLCSP封装的内部电路。
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公开(公告)号:US08569861B2
公开(公告)日:2013-10-29
申请号:US12975847
申请日:2010-12-22
申请人: Alan O'Donnell , Santiago Iriarte , Mark J. Murphy , Colin Lyden , Gary Casey , Eoin Edward English
发明人: Alan O'Donnell , Santiago Iriarte , Mark J. Murphy , Colin Lyden , Gary Casey , Eoin Edward English
IPC分类号: H01L29/86 , H01L29/8605
CPC分类号: G01N27/226 , B81B7/00 , B81B7/007 , B81B2201/0214 , G01N27/26 , G01N27/4148 , H01F17/00 , H01F17/04 , H01L21/82 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/58 , H01L24/05 , H01L24/13 , H01L24/48 , H01L24/94 , H01L25/16 , H01L25/167 , H01L27/0694 , H01L27/14 , H01L27/15 , H01L28/00 , H01L28/10 , H01L28/20 , H01L28/60 , H01L28/82 , H01L28/86 , H01L28/90 , H01L31/0392 , H01L31/0525 , H01L31/0547 , H01L31/056 , H01L31/06 , H01L35/00 , H01L35/28 , H01L35/30 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/0557 , H01L2224/32145 , H01L2224/48091 , H01L2224/48265 , H01L2225/06531 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/15788 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H02S10/10 , H02S40/38 , Y02E10/50 , Y02E10/52 , H01L2924/00 , H01L2224/45099 , H01L2224/05552 , H01L2224/85399 , H01L2224/05599
摘要: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.
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