公开(公告)号：US06770500B2

公开(公告)日：2004-08-03

申请号：US10099004

申请日：2002-03-15

申请人： Alessandro Cesare Callegari ,  Christopher P. D'emic ,  Hyungjun Kim ,  Fenton Read McFeely ,  Vijay Narayanan ,  John Jacob Yurkas

发明人： Alessandro Cesare Callegari ,  Christopher P. D'emic ,  Hyungjun Kim ,  Fenton Read McFeely ,  Vijay Narayanan ,  John Jacob Yurkas

IPC分类号： H01L2100

CPC分类号： H01L21/823828 ,  H01L21/28079 ,  H01L21/3003

摘要： A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250° C. and about 500° C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.

摘要翻译： 钝化金属门控CMOS结构的方法，其中金属门控CMOS结构在分子氢气氛中在约250℃至约500℃的温度和至少约200℃的压力下钝化 托尔 本方法提供比通过现有技术的钝化工艺可获得的更低的界面状态密度。

公开(公告)号：US20080311745A1

公开(公告)日：2008-12-18

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, JR. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/44

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US07863083B2

公开(公告)日：2011-01-04

申请号：US12197845

申请日：2008-08-25

申请人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

发明人： Ricky Amos ,  Douglas A. Buchanan ,  Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Supratik Guha ,  Hyungjun Kim ,  Fenton R. McFeely ,  Vijay Narayanan ,  Kenneth P. Rodbell ,  John J. Yurkas

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L21/266 ,  H01L21/425

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/3003

摘要： A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

摘要翻译： 描述了通过使用Re，Rh，Pt，Ir或Ru金属制造CMOS栅电极的方法和包含这种栅电极的CMOS结构。 这些金属的工作功能使其与当前的pFET要求兼容。 例如，金属可以承受生产适当钝化界面而不经历化学变化所需的高氢气压力。 金属在介电层上的热稳定性如SiO 2，Al 2 O 3和其它合适的介电材料使其与后处理温度高达1000℃相兼容。具有Re2（CO）10作为源的低温/低压CVD技术 当Re沉积时使用材料。

公开(公告)号：US20120301706A1

公开(公告)日：2012-11-29

申请号：US13568808

申请日：2012-08-07

申请人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

发明人： Andrew J. Kellock ,  Hyungjun Kim ,  Dae-Gyu Park ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Stephen Rossnagel ,  Oscar Van Der Straten

IPC分类号： C23C16/50 ,  B32B3/26

CPC分类号： C23C16/45536 ,  C23C16/36 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/3141 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76831 ,  Y10T428/24999

摘要： A method of depositing a SiNxCy liner on a porous low thermal conductivity (low-k) substrate by plasma-enhanced atomic layer deposition (PE-ALD), which includes forming a SiNxCy liner on a surface of a low-k substrate having pores on a surface thereon, in which the low-k substrate is repeatedly exposed to a aminosilane-based precursor and a plasma selected from nitrogen, hydrogen, oxygen, helium, and combinations thereof until a thickness of the liner is obtained, and wherein the liner is prevented from penetrating inside the pores of a surface of the substrate. A porous low thermal conductivity substrate having a SiNxCy liner formed thereon by the method is also disclosed.

摘要翻译： 一种通过等离子体增强原子层沉积（PE-ALD）在多孔低热导率（低k）衬底上沉积SiNxCy衬垫的方法，其包括在具有孔的低k衬底的表面上形成SiN xCy衬垫 其中低k衬底反复暴露于基于氨基硅烷的前体和选自氮，氢，氧，氦及其组合的等离子体，直到获得衬垫的厚度，并且其中衬垫是 防止在基板的表面的孔内渗透。 还公开了通过该方法在其上形成SiN xCy衬垫的多孔低热导率衬底。

公开(公告)号：US07211507B2

公开(公告)日：2007-05-01

申请号：US10709865

申请日：2004-06-02

申请人： Derren N. Dunn ,  Hyungjun Kim ,  Stephen M. Rossnagel ,  Soon-Cheon Seo

发明人： Derren N. Dunn ,  Hyungjun Kim ,  Stephen M. Rossnagel ,  Soon-Cheon Seo

IPC分类号： H01L21/285

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of depositing a tantalum-nitride (TaN) diffusion barrier region on low-k materials. The methods include forming a protective layer on the low-k material substrate by performing plasma-enhanced atomic layer deposition (PE-ALD) from tantalum-based precursor and a nitrogen plasma in a chamber. The protective layer has a nitrogen content greater than its tantalum content. A substantially stoichiometric tantalum-nitride layer is then formed by performing PE-ALD from the tantalum-based precursor and a plasma including hydrogen and nitrogen. The invention also includes the tantalum-nitride diffusion barrier region so formed. In one embodiment, the metal precursor includes tantalum penta-chloride (TaCl5). The invention generates a sharp interface between low-k materials and liner materials.

摘要翻译： 在低k材料上沉积氮化钽（TaN）扩散阻挡区域的方法。 所述方法包括通过从钽基前体和室中的氮等离子体进行等离子体增强原子层沉积（PE-ALD）在低k材料衬底上形成保护层。 保护层的氮含量大于其钽含量。 然后通过从钽基前体和包括氢和氮的等离子体中进行PE-ALD形成基本上化学计量的氮化钽层。 本发明还包括如此形成的氮化钽 - 氮化物扩散阻挡区域。 在一个实施方案中，金属前体包括五氯化钽（TaCl 5 N 5）。 本发明在低k材料和衬垫材料之间产生尖锐的界面。

公开(公告)号：US07186446B2

公开(公告)日：2007-03-06

申请号：US10699226

申请日：2003-10-31

申请人： Hyungjun Kim ,  Andrew J. Kellock ,  Stephen M. Rossnagel

发明人： Hyungjun Kim ,  Andrew J. Kellock ,  Stephen M. Rossnagel

IPC分类号： H05H1/24

CPC分类号： C23C16/45542 ,  C23C16/34 ,  C23C16/45525 ,  H01L21/28562 ,  H01L21/76843

摘要： A method to deposit TaN by plasma enhanced layer with various nitrogen content. Using a mixture of hydrogen and nitrogen plasma, the nitrogen content in the film can be controlled from 0 to N/Ta=1.7. By turning off the nitrogen flow during deposition of TaN, a TaN/Ta bilayer is easily grown, which has copper diffusion barrier properties superior to those of a single Ta layer or a single TaN layer.

摘要翻译： 一种用各种氮含量的等离子体增强层沉积TaN的方法。 使用氢和氮等离子体的混合物，膜中的氮含量可以从0到N / Ta = 1.7。 通过在TaN沉积期间关闭氮气流，容易生长TaN / Ta双层，其具有优于单个Ta层或单个TaN层的铜扩散阻挡性能。

公开(公告)号：US07023064B2

公开(公告)日：2006-04-04

申请号：US10710063

申请日：2004-06-16

申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

IPC分类号： H01L29/76

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

公开(公告)号：US20050110144A1

公开(公告)日：2005-05-26

申请号：US10707117

申请日：2003-11-21

申请人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

发明人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。

公开(公告)号：US08404143B2

公开(公告)日：2013-03-26

申请号：US13402365

申请日：2012-02-22

申请人： Hyungjun Kim ,  Richard Wen ,  Bin Hu ,  Minae Tanaka ,  Deepak Mahulikar

发明人： Hyungjun Kim ,  Richard Wen ,  Bin Hu ,  Minae Tanaka ,  Deepak Mahulikar

IPC分类号： C09K13/00

CPC分类号： H01L21/30625 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： The present disclosure provides a concentrate for use in chemical mechanical polishing slurries, and a method of diluting that concentrate to a point of use slurry. The concentrate comprises abrasive, complexing agent, and corrosion inhibitor, and the concentrate is diluted with water and oxidizer. These components are present in amounts such that the concentrate can be diluted at very high dilution ratios, without affecting the polishing performance.

摘要翻译： 本公开提供了用于化学机械抛光浆料的浓缩物，以及将该浓缩物稀释到使用点浆料的方法。 浓缩物包括研磨剂，络合剂和缓蚀剂，浓缩物用水和氧化剂稀释。 这些组分的存在量使得浓缩物可以以非常高的稀释比稀释，而不影响抛光性能。

公开(公告)号：US20120145951A1

公开(公告)日：2012-06-14

申请号：US13402365

申请日：2012-02-22

申请人： Hyungjun Kim ,  Richard Wen ,  Bin Hu ,  Minae Tanaka ,  Deepak Mahulikar

发明人： Hyungjun Kim ,  Richard Wen ,  Bin Hu ,  Minae Tanaka ,  Deepak Mahulikar

IPC分类号： C09K13/00 ,  C09K13/04

CPC分类号： H01L21/30625 ,  C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： The present disclosure provides a concentrate for use in chemical mechanical polishing slurries, and a method of diluting that concentrate to a point of use slurry. The concentrate comprises abrasive, complexing agent, and corrosion inhibitor, and the concentrate is diluted with water and oxidizer. These components are present in amounts such that the concentrate can be diluted at very high dilution ratios, without affecting the polishing performance.

摘要翻译： 本公开提供了用于化学机械抛光浆料的浓缩物，以及将该浓缩物稀释到使用点浆料的方法。 浓缩物包括研磨剂，络合剂和缓蚀剂，浓缩物用水和氧化剂稀释。 这些组分的存在量使得浓缩物可以以非常高的稀释比稀释，而不影响抛光性能。