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    Nanotube array and method for producing a nanotube array
    1.
    发明授权
    Nanotube array and method for producing a nanotube array 失效
    纳米管阵列及其制造方法

    公开(公告)号：US07635867B2

    公开(公告)日：2009-12-22

    申请号：US10476663

    申请日：2002-05-16

    申请人： Andrew Graham ,  Franz Hofmann ,  Johannes Kretz ,  Franz Kreupl ,  Richard Luyken ,  Wolfgang Rösner

    发明人： Andrew Graham ,  Franz Hofmann ,  Johannes Kretz ,  Franz Kreupl ,  Richard Luyken ,  Wolfgang Rösner

    IPC分类号： H01L31/0312

    CPC分类号： H01L51/0048 ,  B82Y10/00 ,  C01B32/05 ,  G01N27/127 ,  G11C13/025 ,  H01L51/0595

    摘要： A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.

    摘要翻译： 纳米管阵列及其制造方法。 纳米管阵列具有衬底，催化剂层，其包括在衬底的表面上的一个或多个子区域，和布置在催化剂层表面上的平行于衬底表面的至少一个纳米管。 所述至少一个纳米管平行于衬底的表面布置，导致至少一个纳米管的平面布置。 因此，本发明的纳米管阵列适用于与传统的硅微电子耦合。 因此，根据本发明，可以将纳米管阵列电连接到宏观半导体电子器件。 此外，根据本发明的纳米管阵列可以在衬底和催化剂层之间具有电绝缘层。 该电绝缘层优选地具有使得至少一个纳米管在其端部部分处于电绝缘层上并且在其中心部分未被覆盖的形貌。 由于至少一个纳米管的表面部分未被覆盖，纳米管的未被覆盖的表面可以用作主动传感器表面。 例如，纳米管的未覆盖表面可以与围绕纳米管阵列的气氛进行操作接触。 在某些气体的存在下，纳米管的电阻显着变化。 因此，由于纳米管是透明和未覆盖的，所以纳米管阵列可用于许多传感器应用中。

    Integrated circuit array
    4.
    发明申请
    Integrated circuit array 审中-公开
    集成电路阵列

    公开(公告)号：US20050224888A1

    公开(公告)日：2005-10-13

    申请号：US11116139

    申请日：2005-04-27

    申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

    发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

    IPC分类号： G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L29/76

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

    摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.

    摘要翻译： 集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。 阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域 和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件 每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层 门区域。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08097915B2

    公开(公告)日：2012-01-17

    申请号：US11139976

    申请日：2005-05-31

    申请人： Wolfgang Rösner ,  Franz Hofmann ,  Michael Specht ,  Martin Städele ,  Johannes Luyken

    发明人： Wolfgang Rösner ,  Franz Hofmann ,  Michael Specht ,  Martin Städele ,  Johannes Luyken

    IPC分类号： H01L31/119

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7393

    摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极 具有栅极电介质层和栅电极的结构。 所述栅极结构布置在所述漏极区域和所述源极区域之间。 提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。