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    Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
    5.
    发明授权
    Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权

    公开(公告)号：US09620498B2

    公开(公告)日：2017-04-11

    申请号：US14341789

    申请日：2014-07-26

    申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    IPC分类号： H01L27/02 ,  H01L27/06

    CPC分类号： H01L27/0255 ,  H01L27/0629

    摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.

    CONFIGURATION OF GATE TO DRAIN (GD) CLAMP AND ESD PROTECTION CIRCUIT FOR POWER DEVICE BREAKDOWN PROTECTION
    6.
    发明申请
    CONFIGURATION OF GATE TO DRAIN (GD) CLAMP AND ESD PROTECTION CIRCUIT FOR POWER DEVICE BREAKDOWN PROTECTION 审中-公开
    闸门配置（GD）钳位和防静电保护电路，用于电源设备断开保护

    公开(公告)号：US20160027771A1

    公开(公告)日：2016-01-28

    申请号：US14341789

    申请日：2014-07-26

    申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    IPC分类号： H01L27/02 ,  H01L27/06

    CPC分类号： H01L27/0255 ,  H01L27/0629

    摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.

    摘要翻译： 一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。 半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列 衬底，其中平行掺杂的柱具有预定的间隙。 掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深深的掺杂阱被设置在U形弯曲部的下方并且被吞噬。

    INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET
    7.
    发明申请
    INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET 有权
    将感测FET集成到分立功率MOSFET中

    公开(公告)号：US20110227155A1

    公开(公告)日：2011-09-22

    申请号：US13149051

    申请日：2011-05-31

    申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 主FET和一个或多个感测FET形成在公共衬底中。 主FET和感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和检测FET的栅极端子。 电隔离可以在主FET的栅极端子和感测FET之间。 与一个或多个感测FET的源极电接触的感测焊盘不与包含感测FET的器件的区域重叠。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection
    8.
    发明申请
    Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
    降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置

    公开(公告)号：US20110076815A1

    公开(公告)日：2011-03-31

    申请号：US12925820

    申请日：2010-10-29

    申请人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

    发明人： Anup Bhalla ,  Xiaobin Wang ,  Wei Wang ,  Yi Su ,  Daniel Ng

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

    摘要翻译： 支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。 该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。 在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件 钝化层。

    INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET
    9.
    发明申请
    INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET 有权
    将感应FET集成到分立功率MOSFET中

    公开(公告)号：US20100320461A1

    公开(公告)日：2010-12-23

    申请号：US12870489

    申请日：2010-08-27

    申请人： Yi Su ,  Anup Bhalla

    发明人： Yi Su ,  Anup Bhalla

    IPC分类号： H01L27/088 ,  H01L21/8234

    CPC分类号： H01L29/7815 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.

    摘要翻译： 半导体器件包括主场效应晶体管（FET）和一个或多个感测FET。 感测FET的晶体管部分被主FET的晶体管包围。 围绕主FET的电隔离结构被配置为将主FET的源极和主体区域与感测FET的源极和体区电气隔离。 感测FET源极焊盘位于主FET的边缘并与感测FET的晶体管部分间隔开。 感测FET源极焊盘通过感测FET探针金属连接到感测FET的晶体管部分。 隔离结构被配置为使得感测FET和感测FET源极焊盘的晶体管部分位于主FET的有效区域之外。

    Integration of a sense FET into a discrete power MOSFET
    10.
    发明授权
    Integration of a sense FET into a discrete power MOSFET 有权
    将感测FET集成到分立功率MOSFET中

    公开(公告)号：US07799646B2

    公开(公告)日：2010-09-21

    申请号：US12098970

    申请日：2008-04-07

    申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

    摘要翻译： 半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。 主FET和一个或多个感测FET形成在公共衬底中。 主FET和每个感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。 在主FET和一个或多个感测FET的栅极端子之间设置电隔离。 本发明的实施例可以应用于N沟道和P沟道MOSFET器件。