公开(公告)号：US06897109B2

公开(公告)日：2005-05-24

申请号：US10864277

申请日：2004-06-09

申请人： Beom-Jun Jin ,  Young-Pil Kim

发明人： Beom-Jun Jin ,  Young-Pil Kim

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10855 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides methods of forming contact holes and integrated circuit devices having the same. A conductive plug is formed on a substrate. A first insulating layer is formed on the conductive plug and a second insulating layer is formed on the first insulating layer. The second insulating layer is etched to expose at least a portion of the first insulating layer and the first insulating layer is etched to expose at least a portion of the conductive plug.

摘要翻译： 本发明提供形成接触孔的方法和具有该接触孔的集成电路器件。 在基板上形成导电塞。 在导电插塞上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。 蚀刻第二绝缘层以暴露第一绝缘层的至少一部分，并且蚀刻第一绝缘层以暴露至少一部分导电插塞。

公开(公告)号：US06818551B2

公开(公告)日：2004-11-16

申请号：US10241026

申请日：2002-09-11

申请人： Beom-Jun Jin ,  Young-Pil Kim

发明人： Beom-Jun Jin ,  Young-Pil Kim

IPC分类号： H01L214763

CPC分类号： H01L27/10855 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides methods of forming contact holes and integrated circuit devices having the same. A conductive plug is formed on a substrate. A first insulating layer is formed on the conductive plug and a second insulating layer is formed on the first insulating layer. The second insulating layer is etched to expose at least a portion of the first insulating layer and the first insulating layer is etched to expose at least a portion of the conductive plug.

摘要翻译： 本发明提供形成接触孔的方法和具有该接触孔的集成电路器件。 在基板上形成导电塞。 在导电插塞上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。 蚀刻第二绝缘层以暴露第一绝缘层的至少一部分，并且蚀刻第一绝缘层以暴露至少一部分导电插塞。

公开(公告)号：US08853010B2

公开(公告)日：2014-10-07

申请号：US13368584

申请日：2012-02-08

申请人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

发明人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L21/339 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

摘要翻译： 半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。 沟道区位于衬底上并位于第一和第二应力产生外延区之间。 栅电极在沟道区上。 沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

公开(公告)号：US20070131159A1

公开(公告)日：2007-06-14

申请号：US11638373

申请日：2006-12-14

申请人： Young-Pil Kim ,  Jin Kim ,  Min-Gu Kang ,  Yu-Gyun Shin ,  Jong-Wook Lee

发明人： Young-Pil Kim ,  Jin Kim ,  Min-Gu Kang ,  Yu-Gyun Shin ,  Jong-Wook Lee

IPC分类号： C30B13/00 ,  C30B19/00 ,  C30B28/08 ,  C30B23/00

CPC分类号： C30B25/18 ,  C30B29/06 ,  C30B29/08 ,  C30B33/12

摘要： A method for growing an epitaxial layer includes obtaining a semiconductor substrate having a plurality of insulating and conductive surfaces, adsorbing a first source gas into the plurality of conductive surfaces to grow a first epitaxial layer thereon, such that the first epitaxial layer has lateral portions overhanging the insulating surfaces, etching the first epitaxial layer to form an etched epitaxial layer, such that the etched epitaxial layer has curved surfaces, and supplying a second source gas to trigger additional epitaxial growth in the etched epitaxial layer.

摘要翻译： 一种用于生长外延层的方法包括获得具有多个绝缘和导电表面的半导体衬底，将第一源气体吸附到多个导电表面中以在其上生长第一外延层，使得第一外延层具有悬垂的侧向部分 蚀刻第一外延层以形成蚀刻的外延层，使得蚀刻的外延层具有弯曲表面，并且提供第二源气体以触发蚀刻的外延层中的另外的外延生长。

公开(公告)号：US07176533B2

公开(公告)日：2007-02-13

申请号：US10982113

申请日：2004-11-04

申请人： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

发明人： Eun-Ae Chung ,  Myoung-Bum Lee ,  Young-Pil Kim ,  Jin-Gyun Kim ,  Bean-Jun Jin

IPC分类号： H01L29/76

CPC分类号： H01L21/76877 ,  H01L21/2257 ,  H01L21/28525 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

摘要翻译： 形成半导体器件可以包括在包括其导电区域的半导体衬底上形成绝缘层，其中绝缘层具有暴露导电区域的一部分的接触孔。 可以在接触孔中形成多晶硅接触插塞，其中多晶硅接触插塞的至少一部分掺杂有具有小于磷（P）的扩散系数的扩散系数的元件。 还讨论了相关结构。

公开(公告)号：US20060283380A1

公开(公告)日：2006-12-21

申请号：US11398118

申请日：2006-04-05

申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B29/06 ,  C30B15/00

摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

公开(公告)号：US20060079056A1

公开(公告)日：2006-04-13

申请号：US11247412

申请日：2005-10-11

申请人： Young-Pil Kim ,  Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  In-Soo Jung

发明人： Young-Pil Kim ,  Sun-Ghil Lee ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  In-Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/78

摘要： A semiconductor structure including a SiGe layer and a method of fabricating the same are provided. The structure includes a silicon layer heavily doped with impurities. A SiGe layer is disposed on the silicon layer. A strained silicon layer is disposed on the SiGe layer. The impurities may be boron. The boron in the silicon layer may have a concentration of 1016 to 1020/cm3. Boron in the SiGe layer, diffused from the silicon substrate or directly doped, may suppress movement of misfit dislocation occurring in the SiGe layer toward the surface, thereby reducing a threading dislocation density near the surface of the strained silicon layer.

摘要翻译： 提供了包括SiGe层的半导体结构及其制造方法。 该结构包括重掺杂杂质的硅层。 SiGe层设置在硅层上。 应变硅层设置在SiGe层上。 杂质可以是硼。 硅层中的硼可以具有10 16至10 20 / cm 3的浓度。 在SiGe层中从硅衬底扩散或直接掺杂的硼可以抑制SiGe层中发生的失配位错的移动朝向表面，由此降低应变硅层表面附近的穿透位错密度。

公开(公告)号：US08119486B2

公开(公告)日：2012-02-21

申请号：US12984176

申请日：2011-01-04

申请人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

发明人： Young-Pil Kim ,  Eun-Ae Chung ,  Gab-Jin Nam ,  Hee-Don Hwang ,  Ji-Young Min

IPC分类号： H01L21/336

CPC分类号： H01L27/10876 ,  H01L29/66628

摘要： A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

摘要翻译： 根据示例实施例的方法包括在衬底中形成隔离区域，所述隔离区限定活性区域。 去除有源区域和隔离区域的期望区域，从而形成凹槽沟槽到期望的深度。 凹槽沟槽是雾化的，以具有与活性区域接触的第一区域和与隔离区域接触的第二区域。 凹槽沟槽的底面的宽度小于其顶面的宽度。 有源区域和隔离区域被退火以提高凹槽通道沟槽的底面。 第一区域的底面的面积增加。 第一区域的底面的深度减小。

公开(公告)号：US07867865B2

公开(公告)日：2011-01-11

申请号：US12166575

申请日：2008-07-02

申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

公开(公告)号：US20090239348A1

公开(公告)日：2009-09-24

申请号：US12478345

申请日：2009-06-04

申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

IPC分类号： H01L21/336

CPC分类号： C30B29/06 ,  C30B15/00

摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。