公开(公告)号：US6084279A

公开(公告)日：2000-07-04

申请号：US831287

申请日：1997-03-31

申请人： Bich-Yen Nguyen ,  J. Olufemi Olowolafe ,  Bikas Maiti ,  Olubunmi Adetutu ,  Philip J. Tobin

发明人： Bich-Yen Nguyen ,  J. Olufemi Olowolafe ,  Bikas Maiti ,  Olubunmi Adetutu ,  Philip J. Tobin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L23/31 ,  H01L29/49 ,  H01L21/338

CPC分类号： H01L27/11 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/28568 ,  H01L21/76895 ,  H01L21/82345 ,  H01L23/3171 ,  H01L29/4925 ,  H01L29/4966 ,  H01L2924/0002

摘要： Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

摘要翻译： 金属半导体氮化物栅电极（40,70）形成用于半导体器件（60）。 栅电极（40,70）可以通过溅射沉积，低压化学气相沉积（LPCVD）或等离子体增强化学气相沉积（PECVD）来形成。 预期这些材料将类似于含硅化合物蚀刻，并且可以在传统的基于卤化物的蚀刻化学中进行蚀刻。 金属半导体氮化物栅电极（40,70）相对稳定，可以形成为比传统栅极电极（40,70）更靠近工作功能，并且靠近用于衬底（12）的材料的带隙中间的功函数。

公开(公告)号：US5543635A

公开(公告)日：1996-08-06

申请号：US455268

申请日：1995-05-31

申请人： Bich-Yen Nguyen ,  Thomas F. McNelly ,  Philip J. Tobin ,  James D. Hayden

发明人： Bich-Yen Nguyen ,  Thomas F. McNelly ,  Philip J. Tobin ,  James D. Hayden

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L29/76 ,  H01L29/04 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/66765 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78678 ,  Y10S148/109

摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。

公开(公告)号：US4987102A

公开(公告)日：1991-01-22

申请号：US445220

申请日：1989-12-04

申请人： Bich-Yen Nguyen ,  Jen-Jiang Lee ,  Hoang K. Nguyen ,  Young Limb ,  Philip J. Tobin

发明人： Bich-Yen Nguyen ,  Jen-Jiang Lee ,  Hoang K. Nguyen ,  Young Limb ,  Philip J. Tobin

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/318

CPC分类号： H01L21/02164 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/318 ,  H01L21/3185

摘要： A method is described for the formation of high purity thin films on a semiconductor substrate. In the preferred embodiment of the invention a thin film is formed on a semiconductor substrate in a plasma enhanced chemical vapor deposition system. Energized silicon ions are obtained by mass analysis and are accelerated into a hydrogen-free plasma. A reaction occurs between energized atoms within the plasma and the energized silicon ions resulting in the deposition of a thin film on the semiconductor substrate.

公开(公告)号：US5208189A

公开(公告)日：1993-05-04

申请号：US769049

申请日：1991-09-30

申请人： Bich-Yen Nguyen ,  Philip J. Tobin

发明人： Bich-Yen Nguyen ,  Philip J. Tobin

IPC分类号： H01L21/318 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L29/51

CPC分类号： H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L29/518 ,  Y10S148/025 ,  Y10S148/043 ,  Y10S148/081 ,  Y10S148/118

摘要： Defects in a thin dielectric layer of a semiconductor device are plugged by a discontinuous layer to maintain integrity of the dielectric without degrading the reliability of the device. In one form of the invention, a semiconductor device (10) includes an oxide layer (14) formed on a substrate material (12). Growth of a nitride layer (18), using CVD techniques, is initiated in any defects (16) in the oxide layer, but growth is terminated prior to entering a continuous growth stage. By plugging the defects with nitride without forming a continuous nitride layer, defect density in thin oxides is reduced without experiencing disadvantages associated with thick oxide-nitride stacks. The invention is also applicable to plugging defects in dielectric layers other than oxide. Furthermore, growth of a discontinuous layer may be achieved with a material other than a nitride using CVD techniques.

公开(公告)号：US4927780A

公开(公告)日：1990-05-22

申请号：US415685

申请日：1989-10-02

申请人： Scott S. Roth ,  Bich-Yen Nguyen ,  Philip J. Tobin ,  Wayne Ray ,  E. Petyr Wachholz ,  Glenn Wissen

发明人： Scott S. Roth ,  Bich-Yen Nguyen ,  Philip J. Tobin ,  Wayne Ray ,  E. Petyr Wachholz ,  Glenn Wissen

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/7621

摘要： An improved LOCOS isolation process is disclosed wherein an oxidizable layer is conformably dieposited to overlie a silicon nitride oxidation mask. In accordance with one embodiment of the invention, a composite layer comprising a buffer layer and an oxidation resistant material is patterned to form an oxidation mask on a silicon substrate. A layer of an oxidizable material is conformably deposited to overlie the oxidation mask. During the oxidation process used to form electrical isolation structures in the substrate, a substantial reduction in lateral oxidation encroachment is realized.

公开(公告)号：US5539216A

公开(公告)日：1996-07-23

申请号：US329925

申请日：1994-10-27

申请人： Bich-Yen Nguyen ,  Marius Orlowski ,  Philip J. Tobin ,  Jim Hayden ,  Jack Higman

发明人： Bich-Yen Nguyen ,  Marius Orlowski ,  Philip J. Tobin ,  Jim Hayden ,  Jack Higman

IPC分类号： H01L27/11 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/78696 ,  H01L27/1108 ,  Y10S257/915

摘要： A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

摘要翻译： 单片半导体本体（26）位于形成在绝缘层（14）中的开口（16）中。 单片半导体本体（26）包括填充绝缘层（14）中的开口（16）并接触半导体区域（12）的细长区域（20）。 单片半导体本体（26）还包括覆盖细长区域（20）的表面区域（24）和邻近开口（16）的绝缘层（14）的表面（22）的一部分。 通过首先将半导体材料层沉积到开口（16）中，然后平坦化绝缘层（14）的表面来制造单片半导体本体（26）。 接下来，进行选择性沉积工艺以使用开口（16）中的半导体材料形成表面区域（24）作为成核位置。 表面区域（24）的曲率半径由选择性沉积过程中受控过度生长的量决定。

公开(公告)号：US4897364A

公开(公告)日：1990-01-30

申请号：US315866

申请日：1989-02-27

申请人： Bich-Yen Nguyen ,  Philip J. Tobin ,  Shih-Wei Sun ,  Michael Woo

发明人： Bich-Yen Nguyen ,  Philip J. Tobin ,  Shih-Wei Sun ,  Michael Woo

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76216

摘要： An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitride mask with the polysilicon providing an etching endpoint during the anisotropic etching used for sidewall formation. In one embodiment of the invention a silicon substrate is provided having a pad oxide formed on its surface and a first polysilicon stress-relief buffer layer formed overlying the pad oxide. A first nitride layer, to be used for oxidation masking during field oxide growth, is deposited overlying the first polysilicon layer. Next, a second polysilicon, etch-resistant buffer layer is deposited overlying the first nitride layer.The first nitride layer and second polysilicon layer are patterned by conventional lithography while the first polysilicon and pad oxide layers remained unpatterned. A second nitride layer is deposited overlying the patterned second polysilicon layer and exposed regions of the first polysilicon layer. Sidewalls are formed on the edges of the patterned first nitride and second polysilicon layers by anisotropically etching the second nitride layer using the first and second polysilicon layers as etching endpoints. Finally, the field oxide is grown by conventional methods. The grown field oxide exhibits reduced bird's beak length, and the resulting field separation is not limited by optical lithography resolution.

摘要翻译： 公开了一种用于形成场氧化物的改进的LOCOS器件隔离方法，其具有可控制和均匀的叶片氧化掩模侧壁框架的优点。 该优点通过使用覆盖氮化物掩模的多晶硅层来实现，其中多晶硅在用于侧壁形成的各向异性蚀刻期间提供蚀刻终点。 在本发明的一个实施例中，提供硅衬底，其具有在其表面上形成的衬垫氧化物和形成在衬垫氧化物上的第一多晶硅应力释放缓冲层。 在场氧化物生长期间用于氧化掩蔽的第一氮化物层沉积在第一多晶硅层上。 接下来，沉积覆盖第一氮化物层的第二多晶硅，耐蚀刻缓冲层。 第一氮化物层和第二多晶硅层通过常规光刻图案化，而第一多晶硅和衬垫氧化物层保持未图案化。 第二氮化物层沉积在图案化的第二多晶硅层和第一多晶硅层的暴露区域上。 通过使用第一和第二多晶硅层作为蚀刻终点通过各向异性蚀刻第二氮化物层，在图案化的第一氮化物和第二多晶硅层的边缘上形成侧壁。 最后，通过常规方法生长场氧化物。 生长的田间氧化物表现出减少的鸟的喙长度，并且所得到的场分离不受光学光刻分辨率的限制。

公开(公告)号：US07029980B2

公开(公告)日：2006-04-18

申请号：US10670928

申请日：2003-09-25

申请人： Chun-Li Liu ,  Marius K. Orlowski ,  Matthew W. Stoker ,  Philip J. Tobin ,  Mariam G. Sadaka ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn G. Thomas ,  Ted R. White

发明人： Chun-Li Liu ,  Marius K. Orlowski ,  Matthew W. Stoker ,  Philip J. Tobin ,  Mariam G. Sadaka ,  Alexander L. Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean ,  Shawn G. Thomas ,  Ted R. White

IPC分类号： H01L21/331

CPC分类号： H01L29/161 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/1054 ,  Y10S438/933

摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.

摘要翻译： 用于在SOI衬底的模板层材料中注入空位的空位注入工艺。 模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。 然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。 进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。 一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。 空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

公开(公告)号：US06362071B1

公开(公告)日：2002-03-26

申请号：US09542706

申请日：2000-04-05

申请人： Bich-Yen Nguyen ,  William J. Taylor, Jr. ,  Philip J. Tobin ,  David L. O'Meara ,  Percy V. Gilbert ,  Yeong-Jyh T. Lii ,  Victor S. Wang

发明人： Bich-Yen Nguyen ,  William J. Taylor, Jr. ,  Philip J. Tobin ,  David L. O'Meara ,  Percy V. Gilbert ,  Yeong-Jyh T. Lii ,  Victor S. Wang

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/823481

摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.

摘要翻译： 根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。 沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。 在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。 所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。 在有源区域内形成具有相反极性的晶体管（721,723）。

公开(公告)号：US5510278A

公开(公告)日：1996-04-23

申请号：US300770

申请日：1994-09-06

申请人： Bich-Yen Nguyen ,  Thomas F. McNelly ,  Philip J. Tobin ,  James D. Hayden

发明人： Bich-Yen Nguyen ,  Thomas F. McNelly ,  Philip J. Tobin ,  James D. Hayden

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L21/786

CPC分类号： H01L29/66765 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78678 ,  Y10S148/109

摘要： An under-gated thin film transistor (54) having low leakage current and a high on/off current ratio is formed using a composite layer (40) of semiconducting material. In one embodiment a composite layer (40) of semiconducting layer is formed by depositing two distinct layers (34, 38) of semiconducting material over the transistor gate electrode (18). The composite layer (40) is then patterned and implanted with ions to form a source region (46) and a drain region (48) within the composite layer (40), and to define a channel region (50) and an offset drain region (52) within the composite layer (40).

摘要翻译： 使用半导体材料的复合层（40）形成具有低漏电流和高导通/截止电流比的欠门控薄膜晶体管（54）。 在一个实施例中，通过在晶体管栅电极（18）上沉积半导体材料的两个不同的层（34,38）形成半导体层的复合层（40）。 然后将复合层（40）图案化并注入离子，以在复合层（40）内形成源区（46）和漏区（48），并且限定沟道区（50）和偏移漏区 （52）内。