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公开(公告)号：US09326370B2
公开(公告)日：2016-04-26
申请号：US13852630
申请日：2013-03-28
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yusuke Murai , Sou Hoshi , Nobuaki Yamashita
CPC classification number: H05K1/025 , H01L2224/16225 , H05K1/0225 , H05K1/0243 , H05K1/181 , H05K2201/09263 , H05K2201/093 , H05K2201/09709
Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.
Abstract translation: 提供了能够在保持功率图案和接地图案的低电阻值的同时增加功率图案和接地图案的电感值的印刷电路板。 印刷电路板包括：印刷电路板，包括：功率层，其中形成有功率图案; 以及其中形成有接地图案的接地层。 在印刷电路板上安装作为半导体器件的LSI和作为电源部件的LSI。 接地图形具有与从印刷电路板的表面垂直的方向观察时与功率图案重叠的第一接地区域。 在第一接地区域中形成至少一个缺陷部分。 在第一接地区域中，缺陷部分形成比功率图形更窄的区域。
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公开(公告)号：US20160143133A1
公开(公告)日：2016-05-19
申请号：US14944051
申请日：2015-11-17
Applicant: CANON KABUSHIKI KAISHA
Inventor： Hiroyuki Miyake , Yusuke Murai , Kiyoshi Sekiguchi
IPC: H05K1/02 , H05K1/11 , H05K1/18 , H01L23/498
CPC classification number: H05K1/0298 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/112 , H05K1/113 , H05K1/181 , H05K3/3436 , H05K2201/09227 , H05K2201/09418 , H01L2924/00
Abstract: A printed wiring board includes conductive layers laminated with insulator layers interposed. A land group including a plurality of lands arranged with intervals between each other, is formed in a rectangular region on a surface layer, among the plurality of conductive layers, when viewed in a direction perpendicular to the surface layer. The land group is arrayed in a triangular lattice manner. The land group is arranged so that a smallest angle, among angles formed between one side of the rectangular region and respective three sides of the triangular lattice, is 7° or more and 23° or less.
Abstract translation: 印刷电路板包括层叠有绝缘体层的导电层。 当在垂直于表面层的方向观察时，在多个导电层中的表层上的矩形区域中形成包括彼此间隔布置的多个焊盘的焊盘组。 陆地组以三角格子排列。 所述焊盘组的布置使得在所述矩形区域的一侧和所述三角形格子的相应三个侧面之间形成的角度之中的最小角度为7°以上且23°以下。
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公开(公告)号：US20140268586A1
公开(公告)日：2014-09-18
申请号：US14198718
申请日：2014-03-06
Applicant: CANON KABUSHIKI KAISHA
Inventor： Sou Hoshi , Nobuaki Yamashita , Yusuke Murai
CPC classification number: H05K1/0224 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2223/6655 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/06135 , H01L2224/131 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2924/00014 , H01L2924/10162 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H05K1/0231 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/4644 , H05K2201/09263 , H05K2201/09672 , H01L2224/45099 , H01L2924/014 , H01L2924/00
Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.
Abstract translation: 半导体封装的衬底包括形成在表面层中的导体图案，并且电连接到半导体元件的电源端子和接地端子之外的一个端子。 基板还在表面层中包括布置成与导体图案分离的导体图案，以及形成为具有比导体图案的布线宽度更薄的布线宽度的导体图案，并将导体图案与 导体图案。 衬底还包括形成在内层中的导体图案，其通过电介质面对导体图案，并且与另一个端子电连接到电源端子和半导体元件的接地端子之外。
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公开(公告)号：US09345126B2
公开(公告)日：2016-05-17
申请号：US14198718
申请日：2014-03-06
Applicant: CANON KABUSHIKI KAISHA
Inventor： Sou Hoshi , Nobuaki Yamashita , Yusuke Murai
CPC classification number: H05K1/0224 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2223/6655 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/06135 , H01L2224/131 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2924/00014 , H01L2924/10162 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H05K1/0231 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/4644 , H05K2201/09263 , H05K2201/09672 , H01L2224/45099 , H01L2924/014 , H01L2924/00
Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.
Abstract translation: 半导体封装的衬底包括形成在表面层中的导体图案，并且电连接到半导体元件的电源端子和接地端子之外的一个端子。 基板还在表面层中包括布置成与导体图案分离的导体图案，以及形成为具有比导体图案的布线宽度更薄的布线宽度的导体图案，并将导体图案与 导体图案。 衬底还包括形成在内层中的导体图案，其通过电介质面对导体图案，并且与另一个端子电连接到电源端子和半导体元件的接地端子之外。
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公开(公告)号：US09084364B2
公开(公告)日：2015-07-14
申请号：US13916443
申请日：2013-06-12
Applicant: CANON KABUSHIKI KAISHA
Inventor： Sou Hoshi , Nobuaki Yamashita , Yusuke Murai , Tohru Ohsaka
CPC classification number: H05K1/181 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H05K1/0228 , H05K1/0262 , H05K2201/09309 , H05K2201/10689 , Y02P70/611 , H01L2924/00012
Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.
Abstract translation: 在印刷电路板的表面层上，施加有不同直流电压的主电源图案设置在第二区域中。 电源图案设置在表面层上，并且电源图案从主电源图案被引导到第一区域。 电源模式连接第二区域的端子组的电源端子。 电源模式将第一区域中的端子组之间的电源端子连接起来。 半导体封装的端子组的电源端子通过电源图案电连接到主电源图案。 因此，电位波动减小，辐射噪声被抑制，并且印刷电路板的层数减少。
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Patent Agency Ranking
公开(公告)号：US09894751B2
公开(公告)日：2018-02-13
申请号：US14944540
申请日：2015-11-18
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yusuke Murai , Shoji Matsumoto , Takashi Numagi , Hiroyuki Yamaguchi , Nobuaki Yamashita
CPC classification number: H05K1/0225 , H05K1/0231 , H05K1/0234 , H05K1/115
Abstract: First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.
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公开(公告)号：US09693450B2
公开(公告)日：2017-06-27
申请号：US14944051
申请日：2015-11-17
Applicant: CANON KABUSHIKI KAISHA
Inventor： Hiroyuki Miyake , Yusuke Murai , Kiyoshi Sekiguchi
IPC: H05K1/11 , H05K1/02 , H01L23/498 , H05K1/18
CPC classification number: H05K1/0298 , H01L23/49822 , H01L23/49838 , H01L2924/0002 , H05K1/112 , H05K1/113 , H05K1/181 , H05K3/3436 , H05K2201/09227 , H05K2201/09418 , H01L2924/00
Abstract: A printed wiring board includes conductive layers laminated with insulator layers interposed. A land group including a plurality of lands arranged with intervals between each other, is formed in a rectangular region on a surface layer, among the plurality of conductive layers, when viewed in a direction perpendicular to the surface layer. The land group is arrayed in a triangular lattice manner. The land group is arranged so that a smallest angle, among angles formed between one side of the rectangular region and respective three sides of the triangular lattice, is 7° or more and 23° or less.
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公开(公告)号：US20160157336A1
公开(公告)日：2016-06-02
申请号：US14944540
申请日：2015-11-18
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yusuke Murai , Shoji Matsumoto , Takashi Numagi , Hiroyuki Yamaguchi , Nobuaki Yamashita
CPC classification number: H05K1/0225 , H05K1/0231 , H05K1/0234 , H05K1/115
Abstract: First and second semiconductor devices and first and second bypass circuits are mounted on a printed wiring board. The first bypass circuit and the second bypass circuit are provided closer to the first semiconductor device and to the second semiconductor device, respectively. The first bypass circuit has one end connected to a power plane through a first power supply via and the other end connected to a ground plane through a first ground via. The second bypass circuit has one end connected to the power plane through a second power supply via and the other end connected to the ground plane through a second ground via. The ground plane has a slit between the connecting portions of the first and second ground vias to increase the impedance between the connecting portions of the first and the second ground vias. Thus, jitters caused by power supply noise can be reduced.
Abstract translation: 第一和第二半导体器件以及第一和第二旁路电路安装在印刷线路板上。 第一旁路电路和第二旁路电路分别靠近第一半导体器件和第二半导体器件设置。 第一旁路电路的一端通过第一电源通路连接到电源平面，另一端通过第一接地通孔连接到接地平面。 第二旁路电路的一端通过第二电源通路连接到电源平面，另一端通过第二接地通孔连接到接地平面。 接地平面在第一和第二接地通孔的连接部分之间具有狭缝，以增加第一和第二接地通路的连接部分之间的阻抗。 因此，可以减少由电源噪声引起的抖动。
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公开(公告)号：US20130343024A1
公开(公告)日：2013-12-26
申请号：US13916443
申请日：2013-06-12
Applicant: CANON KABUSHIKI KAISHA
Inventor： Sou Hoshi , Nobuaki Yamashita , Yusuke Murai , Tohru Ohsaka
IPC: H05K1/18
CPC classification number: H05K1/181 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H05K1/0228 , H05K1/0262 , H05K2201/09309 , H05K2201/10689 , Y02P70/611 , H01L2924/00012
Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.
Abstract translation: 在印刷电路板的表面层上，施加有不同直流电压的主电源图案设置在第二区域中。 电源图案设置在表面层上，并且电源图案从主电源图案被引导到第一区域。 电源模式连接第二区域的端子组的电源端子。 电源模式将第一区域中的端子组之间的电源端子连接起来。 半导体封装的端子组的电源端子通过电源图案电连接到主电源图案。 因此，电位波动减小，辐射噪声被抑制，并且印刷电路板的层数减少。
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公开(公告)号：US20130265726A1
公开(公告)日：2013-10-10
申请号：US13852630
申请日：2013-03-28
Applicant: CANON KABUSHIKI KAISHA
Inventor： Yusuke Murai , Sou Hoshi , Nobuaki Yamashita
CPC classification number: H05K1/025 , H01L2224/16225 , H05K1/0225 , H05K1/0243 , H05K1/181 , H05K2201/09263 , H05K2201/093 , H05K2201/09709
Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.
Abstract translation: 提供了能够在保持功率图案和接地图案的低电阻值的同时增加功率图案和接地图案的电感值的印刷电路板。 印刷电路板包括：印刷电路板，包括：功率层，其中形成有功率图案; 以及其中形成有接地图案的接地层。 在印刷电路板上安装作为半导体器件的LSI和作为电源部件的LSI。 接地图形具有与从印刷电路板的表面垂直的方向观察时与功率图案重叠的第一接地区域。 在第一接地区域中形成至少一个缺陷部分。 在第一接地区域中，缺陷部分形成比功率图形更窄的区域。
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