公开(公告)号：US07902650B2

公开(公告)日：2011-03-08

申请号：US12464334

申请日：2009-05-12

申请人： Chia Chien Hu ,  Chao Cheng Liu ,  Chien Liu ,  Chih Ming Chung

发明人： Chia Chien Hu ,  Chao Cheng Liu ,  Chien Liu ,  Chih Ming Chung

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

摘要翻译： 半导体封装包括载体，芯片，加强件和密封剂。 芯片设置在载体上。 加强件设置在芯片周围，直接接触载体，并安装在载体上。 密封剂适于密封芯片和加强件。

公开(公告)号：US20090289339A1

公开(公告)日：2009-11-26

申请号：US12464334

申请日：2009-05-12

申请人： Chia Chien HU ,  Chao Cheng Liu ,  Chien Liu ,  Chih Ming Chung

发明人： Chia Chien HU ,  Chao Cheng Liu ,  Chien Liu ,  Chih Ming Chung

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

摘要翻译： 半导体封装包括载体，芯片，加强件和密封剂。 芯片设置在载体上。 加强件设置在芯片周围，直接接触载体，并安装在载体上。 密封剂适于密封芯片和加强件。

公开(公告)号：US20090289338A1

公开(公告)日：2009-11-26

申请号：US12464315

申请日：2009-05-12

申请人： Chia Chien HU ,  Chao Cheng Liu ,  Chien Liu ,  Chih Ming Chung

发明人： Chia Chien HU ,  Chao Cheng Liu ,  Chien Liu ,  Chih Ming Chung

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/83 ,  H01L2924/00

摘要： A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

公开(公告)号：US20090278242A1

公开(公告)日：2009-11-12

申请号：US12428277

申请日：2009-04-22

申请人： Yao-Kai Chuang ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

发明人： Yao-Kai Chuang ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip.

摘要翻译： 提供了包括引线框架，芯片封装，第二芯片和第二模塑料的堆叠式芯片封装结构。 引线框架包括彼此绝缘的多个第一引线和第二引线。 第一引线具有第一上表面，并且第二引线具有与第一上表面不共面的第二上表面。 芯片封装设置在第一引线上并且包括基板，第一芯片和第一模塑料。 第二芯片堆叠在芯片封装上并电连接到第二引线。 第二模塑料设置在引线框架上，并且填充在第一引线和用于封装芯片封装和第二芯片的第二引线之间。

公开(公告)号：US20090267210A1

公开(公告)日：2009-10-29

申请号：US12428762

申请日：2009-04-23

申请人： Yao-Kai CHUANG ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

发明人： Yao-Kai CHUANG ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/49575 ,  H01L21/4832 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85001 ,  H01L2225/0651 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged along an inner row and an outer row with respect to the die pad. The first die is fixed on the first die and electrically connected to the first contact pads by wire-bonding. The second die is fixed on the first die and electrically connected to the second contact pads by wire-bonding. The molding compound covers the second die, the first die, the die pad, the first contact pads and the second contact pads. The bottoms of the die pad, the first contact pads and the second contact pads are exposed at the bottom surface of the molding compound.

摘要翻译： 提供一种集成电路封装及其制造方法。 封装包括管芯焊盘，多个第一和第二接触焊盘，第一管芯，第二管芯和模塑料。 与芯片焊盘的至少一侧相邻的接触焊盘相对于管芯焊盘沿着内排和外排布置。 第一管芯固定在第一管芯上，并通过引线接合电连接到第一接触焊盘。 第二管芯固定在第一管芯上，并通过引线接合电连接到第二接触焊盘。 模塑料覆盖第二模具，第一模具，芯片焊盘，第一接触焊盘和第二接触焊盘。 芯片焊盘的底部，第一接触焊盘和第二接触焊盘在模塑料的底表面露出。

公开(公告)号：US07834469B2

公开(公告)日：2010-11-16

申请号：US12428277

申请日：2009-04-22

申请人： Yao-Kai Chuang ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

发明人： Yao-Kai Chuang ,  Chien Liu ,  Chih-Ming Chung ,  Chao-Cheng Liu

IPC分类号： H01L23/29

CPC分类号： H01L23/49548 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip.

摘要翻译： 提供了包括引线框架，芯片封装，第二芯片和第二模塑料的堆叠式芯片封装结构。 引线框架包括彼此绝缘的多个第一引线和第二引线。 第一引线具有第一上表面，并且第二引线具有与第一上表面不共面的第二上表面。 芯片封装设置在第一引线上并且包括基板，第一芯片和第一模塑料。 第二芯片堆叠在芯片封装上并电连接到第二引线。 第二模塑料设置在引线框架上，并且填充在第一引线和用于封装芯片封装和第二芯片的第二引线之间。

公开(公告)号：US20090278243A1

公开(公告)日：2009-11-12

申请号：US12429476

申请日：2009-04-24

申请人： Yao-Kai Chuang ,  Chih-Ming Chung ,  Chien Liu ,  Chao-Cheng Liu

发明人： Yao-Kai Chuang ,  Chih-Ming Chung ,  Chien Liu ,  Chao-Cheng Liu

IPC分类号： H01L23/52 ,  H01L21/98

CPC分类号： H01L21/4832 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed on the die pads respectively, and are electrically connected to the leads by wire bonding. The third chip traverses the first chip and the second chip, and is electrically connected to the first chip and the second chip respectively. The insulating material is disposed on the chip carrier for encapsulating the first chip, the second chip and the third chip, and fills among the die pads and the leads.

摘要翻译： 提供了包括芯片载体，第一芯片，第二芯片，第三芯片和绝缘材料的堆叠型芯片封装结构。 芯片载体包括两个管芯焊盘和围绕焊盘的多个引线。 第一芯片和第二芯片分别设置在芯片焊盘上，并且通过引线接合电连接到引线。 第三芯片穿过第一芯片和第二芯片，分别电连接到第一芯片和第二芯片。 绝缘材料设置在芯片载体上，用于封装第一芯片，第二芯片和第三芯片，并且填充在芯片焊盘和引线之间。

公开(公告)号：US20060281223A1

公开(公告)日：2006-12-14

申请号：US11322676

申请日：2005-12-30

申请人： Chien Liu ,  Chih-Ming Chung

发明人： Chien Liu ,  Chih-Ming Chung

IPC分类号： H01L21/58

CPC分类号： H01L21/4846 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： The invention achieves the above-identified object by providing a packaging, comprising steps of: (a) providing an integrated circuit unit having an active surface, a plurality of bumps disposed thereon; (b) providing a substrate having a first surface and a second surface, a plurality of pads disposed on the first surface, a metal layer formed on the second surface; (c) forming an integrated circuit assembly by connecting the bumps and pads; and (d) forming a plurality of metallic pieces by etching the metal layer.

摘要翻译： 本发明通过提供一种包装来实现上述目的，包括以下步骤：（a）提供具有活性表面的集成电路单元，其上设置有多个凸块; （b）提供具有第一表面和第二表面的基底，设置在第一表面上的多个垫，形成在第二表面上的金属层; （c）通过连接凸起和焊盘形成集成电路组件; 和（d）通过蚀刻金属层形成多个金属片。

公开(公告)号：US08384204B2

公开(公告)日：2013-02-26

申请号：US12683613

申请日：2010-01-07

申请人： Chien Liu ,  Chih-Ming Chung

发明人： Chien Liu ,  Chih-Ming Chung

IPC分类号： H01L23/482 ,  H05K1/09

CPC分类号： H05K3/3452 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/498 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.

摘要翻译： 提供适于与凸块连接的电路载体。 电路载体包括衬底和至少一个接合焊盘。 衬底具有设置在其表面上用于与凸块连接的接合焊盘。 在接合焊盘的表面上设置有棕色氧化物层。

公开(公告)号：US20100213598A1

公开(公告)日：2010-08-26

申请号：US12683613

申请日：2010-01-07

申请人： Chien Liu ,  Chih-Ming Chung

发明人： Chien Liu ,  Chih-Ming Chung

IPC分类号： H01L23/482 ,  H05K1/09

CPC分类号： H05K3/3452 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/498 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.

摘要翻译： 提供适于与凸块连接的电路载体。 电路载体包括衬底和至少一个接合焊盘。 衬底具有设置在其表面上用于与凸块连接的接合焊盘。 在接合焊盘的表面上设置有棕色氧化物层。