摘要:
An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer.
摘要:
An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a light shielding layer disposed on the second surface of the substrate and directly contacting with the conducting layer, wherein the light shielding layer has a light shielding rate of more than about 80% and has at least an opening exposing the conducting layer; and a conducting bump disposed in the opening of the light shielding layer to electrically contact with the conducting layer, wherein all together the light shielding layer and the conducting bump substantially and completely cover the second surface of the substrate.
摘要:
A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.
摘要:
An electronic device including a housing, a circuit board, a first non-metal conductive cushion and a fastening element is provided. The circuit board is disposed in the housing. The first non-metal conductive cushion is disposed between the circuit board and the housing. A potential of the first non-metal conductive cushion is equal to a potential of the housing. The fastening element fastens the circuit board and the non-metal conductive cushion to the housing.
摘要:
The present invention provides a method of manufacturing an LC alignment film utilizing long-throw sputtering. The method includes putting a substrate on a substrate carrier in a chamber, utilizing high-density plasma to bombard a target over the substrate to produce sputtering species, and providing a bias voltage in the chamber. Nearly vertical directional sputtering species are deposited on the surface of the substrate to form an LC alignment film. The distance between the target and the substrate is more than 20 cm.
摘要:
An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.
摘要:
A fastening mechanism suitable for being assembled into a device having a housing is provided. The fastening mechanism includes a post, a latching element, at least a plunger assembly, and an operating element. The latching element has at least an opening, the plunger assembly is disposed at a side of the latching element, and the operating element is in contact with the latching element. The post passes through the opening and presses against the plunger assembly and the post is confined by the latching element when the operating element is in a locking position. The operating element drives the latching element to move horizontally relative to the latching element so as to release the post from confinement and the plunger assembly moves vertically relative to the latching element so as to push the post out of the opening when the operating element moves to an unlocking position.
摘要:
An electronic device including a housing, a circuit board, a first non-metal conductive cushion and a fastening element is provided. The circuit board is disposed in the housing. The first non-metal conductive cushion is disposed between the circuit board and the housing. A potential of the first non-metal conductive cushion is equal to a potential of the housing. The fastening element fastens the circuit board and the non-metal conductive cushion to the housing.
摘要:
A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.