公开(公告)号：US07898075B2

公开(公告)日：2011-03-01

申请号：US12202036

申请日：2008-08-29

申请人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Taek-Hoon Lee

发明人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Taek-Hoon Lee

IPC分类号： H01L23/02 ,  H01L23/04

CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

摘要翻译： 在一个实施例中，本文公开的半导体封装通常可以被表征为包括具有第一凹部的树脂基板，设置在第一凹部的表面上的第一互连，设置在第一凹部中的第一半导体芯片，以及底部填充树脂层 基本上填充第一凹部并覆盖第一半导体芯片的侧表面。 第一半导体芯片电连接到第一互连。

公开(公告)号：US08008771B2

公开(公告)日：2011-08-30

申请号：US12193561

申请日：2008-08-18

申请人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

摘要翻译： 一种半导体芯片封装，包括：半导体芯片，包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US20090065919A1

公开(公告)日：2009-03-12

申请号：US12202036

申请日：2008-08-29

申请人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

发明人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC分类号： H01L23/488

CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

摘要翻译： 在一个实施例中，本文公开的半导体封装通常可以被表征为包括具有第一凹部的树脂基板，设置在第一凹部的表面上的第一互连，设置在第一凹部中的第一半导体芯片，以及底部填充树脂层 基本上填充第一凹部并覆盖第一半导体芯片的侧表面。 第一半导体芯片电连接到第一互连。

公开(公告)号：US08344497B2

公开(公告)日：2013-01-01

申请号：US12240036

申请日：2008-09-29

申请人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L23/48

CPC分类号： H01L23/49541 ,  H01L23/3114 ,  H01L2224/04105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

摘要翻译： 半导体封装可以包括半导体芯片，模制半导体芯片的模制层和跨越半导体芯片和模制层之间的界面延伸并将半导体芯片连接到外部的互连，其中互连的形状是 沿其长度改变。 根据本发明，即使对互连件施加机械应力或热应力，在互连中也不会发生裂纹，也不会断开互连。 因此，提高了半导体封装的可靠性。

公开(公告)号：US20120077311A1

公开(公告)日：2012-03-29

申请号：US13314464

申请日：2011-12-08

申请人： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L21/60

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

摘要： In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

摘要翻译： 在一个实施例中，半导体封装包括第一绝缘体和具有第一有源表面和与第一有源表面相对的第一后表面的第一半导体芯片。 第一半导体芯片设置在第一绝缘体内。 第一活性表面被第一绝缘体暴露。 第一后表面基本上被第一绝缘体包围。 半导体封装包括在第一绝缘体内并邻近第一半导体芯片的一侧的柱。

公开(公告)号：US08093703B2

公开(公告)日：2012-01-10

申请号：US12104333

申请日：2008-04-16

申请人： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L23/00

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

摘要： In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

摘要翻译： 在一个实施例中，半导体封装包括第一绝缘体和具有第一有源表面和与第一有源表面相对的第一后表面的第一半导体芯片。 第一半导体芯片设置在第一绝缘体内。 第一活性表面被第一绝缘体暴露。 第一后表面基本上被第一绝缘体包围。 半导体封装包括在第一绝缘体内并邻近第一半导体芯片的一侧的柱。

公开(公告)号：US20090289359A1

公开(公告)日：2009-11-26

申请号：US12469253

申请日：2009-05-20

申请人： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

发明人： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC分类号： H01L23/498

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 根据本发明总体构思的半导体封装可以包括其上形成有连接端子的一个表面的基底基板和具有覆盖基底基板的成型层的第一封装基板。 模制层面向连接端子的圆周，并且包括分别具有不同尺寸的圆周的第一表面和第二表面的侧表面。

公开(公告)号：US08846446B2

公开(公告)日：2014-09-30

申请号：US13314464

申请日：2011-12-08

申请人： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L21/60 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

摘要： In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

摘要翻译： 在一个实施例中，半导体封装包括第一绝缘体和具有第一有源表面和与第一有源表面相对的第一后表面的第一半导体芯片。 第一半导体芯片设置在第一绝缘体内。 第一活性表面被第一绝缘体暴露。 第一后表面基本上被第一绝缘体包围。 半导体封装包括在第一绝缘体内并邻近第一半导体芯片的一侧的柱。

公开(公告)号：US08154122B2

公开(公告)日：2012-04-10

申请号：US12469253

申请日：2009-05-20

申请人： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

发明人： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 根据本发明总体构思的半导体封装可以包括其上形成有连接端子的一个表面的基底基板和具有覆盖基底基板的成型层的第一封装基板。 模制层面向连接端子的圆周，并且包括分别具有不同尺寸的圆周的第一表面和第二表面的侧表面。

公开(公告)号：US20100013076A1

公开(公告)日：2010-01-21

申请号：US12505606

申请日：2009-07-20

申请人： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

发明人： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC分类号： H01L23/16 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3142 ,  H01L24/19 ,  H01L24/31 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/12105 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2224/83951 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/013 ,  H01L2924/00014

摘要： A semiconductor device package includes a semiconductor chip having a top surface on which a conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other; a first insulating layer covering the top surface of the semiconductor chip and laterally extending to the outside of the semiconductor chip; a fillet member covering a boundary where the side surface of the semiconductor chip and the first insulating layer meet each other; and a molding layer covering the bottom surface of the semiconductor chip, the fillet member, and the first insulating layer.

摘要翻译： 半导体器件封装包括：半导体芯片，其具有设置有导电焊盘的顶表面，与顶表面相对的底面;以及将顶表面和底表面彼此连接的侧表面; 覆盖半导体芯片的顶表面并横向延伸到半导体芯片外部的第一绝缘层; 覆盖半导体芯片的侧表面和第一绝缘层相遇的边界的圆角构件; 以及覆盖半导体芯片的底面，圆角构件和第一绝缘层的成型层。