公开(公告)号：US08344497B2

公开(公告)日：2013-01-01

申请号：US12240036

申请日：2008-09-29

申请人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L23/48

CPC分类号： H01L23/49541 ,  H01L23/3114 ,  H01L2224/04105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

摘要翻译： 半导体封装可以包括半导体芯片，模制半导体芯片的模制层和跨越半导体芯片和模制层之间的界面延伸并将半导体芯片连接到外部的互连，其中互连的形状是 沿其长度改变。 根据本发明，即使对互连件施加机械应力或热应力，在互连中也不会发生裂纹，也不会断开互连。 因此，提高了半导体封装的可靠性。

公开(公告)号：US08008771B2

公开(公告)日：2011-08-30

申请号：US12193561

申请日：2008-08-18

申请人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

发明人： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

摘要翻译： 一种半导体芯片封装，包括：半导体芯片，包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US20090065919A1

公开(公告)日：2009-03-12

申请号：US12202036

申请日：2008-08-29

申请人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

发明人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC分类号： H01L23/488

CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

摘要翻译： 在一个实施例中，本文公开的半导体封装通常可以被表征为包括具有第一凹部的树脂基板，设置在第一凹部的表面上的第一互连，设置在第一凹部中的第一半导体芯片，以及底部填充树脂层 基本上填充第一凹部并覆盖第一半导体芯片的侧表面。 第一半导体芯片电连接到第一互连。

公开(公告)号：US07898075B2

公开(公告)日：2011-03-01

申请号：US12202036

申请日：2008-08-29

申请人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Taek-Hoon Lee

发明人： Chul-Yong Jang ,  Eun-Chul Ahn ,  Pyoung-Wan Kim ,  Taek-Hoon Lee

IPC分类号： H01L23/02 ,  H01L23/04

CPC分类号： H01L23/13 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

摘要： In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

摘要翻译： 在一个实施例中，本文公开的半导体封装通常可以被表征为包括具有第一凹部的树脂基板，设置在第一凹部的表面上的第一互连，设置在第一凹部中的第一半导体芯片，以及底部填充树脂层 基本上填充第一凹部并覆盖第一半导体芯片的侧表面。 第一半导体芯片电连接到第一互连。

公开(公告)号：US07626254B2

公开(公告)日：2009-12-01

申请号：US12121490

申请日：2008-05-15

申请人： Min-Ho O ,  Jong-Ho Lee ,  Eun-Chul Ahn ,  Pyoung-Wan Kim

发明人： Min-Ho O ,  Jong-Ho Lee ,  Eun-Chul Ahn ,  Pyoung-Wan Kim

IPC分类号： H01L23/48

CPC分类号： H01L24/85 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.

摘要翻译： 提供了使用芯片嵌入式插入器基板的半导体封装。 芯片嵌入式插入器基板包括：包括多个芯片焊盘的芯片; 具有安装在其上的芯片并且包括用于重新分配芯片焊盘的多个再分配焊盘的衬底; 用于将芯片焊盘连接到再分配焊盘的接合线; 保护层，其具有用于在掩埋所述芯片和所述基板的同时露出所述再分布焊盘的通孔; 以及通过通孔连接到再分配焊盘的通孔。 包括各种尺寸的芯片的半导体封装使用芯片嵌入式插入器基板来制造。

公开(公告)号：US07888785B2

公开(公告)日：2011-02-15

申请号：US12219263

申请日：2008-07-18

申请人： Eun-Chul Ahn ,  Min-Ho O ,  Jong Ho Lee

发明人： Eun-Chul Ahn ,  Min-Ho O ,  Jong Ho Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/13 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/185 ,  H05K2201/09509 ,  H05K2201/10515 ,  H05K2201/10719 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/01049

摘要： A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package.

摘要翻译： 一种器件包括基底，包括封装的芯片的封装，至少部分地嵌入基底衬底中的封装以及封装上的布线部分，并延伸穿过与封装相邻的基底衬底的至少一部分。

公开(公告)号：US07821139B2

公开(公告)日：2010-10-26

申请号：US11946750

申请日：2007-11-28

申请人： Tae-Joo Hwang ,  Eun-Chul Ahn ,  Tae-Gyeong Chung

发明人： Tae-Joo Hwang ,  Eun-Chul Ahn ,  Tae-Gyeong Chung

IPC分类号： H01L31/00

CPC分类号： H01L24/90 ,  H01L23/3171 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.

摘要翻译： 倒装芯片组件包括半导体芯片，衬底，第一缓冲层，第二缓冲层和导电凸块。 半导体芯片包括与第一区域相邻的第一区域和第二区域。 衬底设置在半导体芯片下方。 第一缓冲层设置在半导体芯片的第一区域和基板之间。 第二缓冲层设置在半导体芯片的第二区域和基板之间。 导电凸块通过第二缓冲层形成并将半导体芯片电连接到基板。

公开(公告)号：US08456012B2

公开(公告)日：2013-06-04

申请号：US12568086

申请日：2009-09-28

申请人： Chang-Woo Shin ,  Hyun-Soo Chung ,  Eun-Chul Ahn ,  Jum-Gon Kim ,  Jin-Ho Chun

发明人： Chang-Woo Shin ,  Hyun-Soo Chung ,  Eun-Chul Ahn ,  Jum-Gon Kim ,  Jin-Ho Chun

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76841 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/12044

摘要： A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.

摘要翻译： 提供一种包括铜焊盘，焊盘阻挡层和金属再分布层的互连结构的半导体器件，其互连结构及其制造方法。 半导体器件包括设置在第一层上的铜焊盘，包括设置在铜焊盘上的钛的焊盘阻挡层，设置在焊盘阻挡层上的无机绝缘层，设置在无机绝缘层上的缓冲层，其中无机绝缘 所述缓冲层暴露所述焊盘阻挡层的一部分，设置在所述暴露的缓冲层上的种子金属层，设置在所述种子金属层上的金属再分配层以及设置在所述金属再分配层上的第一保护层。

公开(公告)号：US20110294260A1

公开(公告)日：2011-12-01

申请号：US13137260

申请日：2011-08-02

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L21/58

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

公开(公告)号：US20100327439A1

公开(公告)日：2010-12-30

申请号：US12875551

申请日：2010-09-03

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L23/485 ,  H01L23/48

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

摘要翻译： 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。