公开(公告)号：US09836391B2

公开(公告)日：2017-12-05

申请号：US14457567

申请日：2014-08-12

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC: G06F12/02 ,  G06F12/0893 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F12/0893 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087 ,  G11C2207/2245

Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

公开(公告)号：US09779804B2

公开(公告)日：2017-10-03

申请号：US15345552

申请日：2016-11-08

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09490014B2

公开(公告)日：2016-11-08

申请号：US14964958

申请日：2015-12-10

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C16/00 ,  G11C16/08 ,  G06F13/42 ,  G11C5/06 ,  G11C7/10 ,  G11C8/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US10224098B2

公开(公告)日：2019-03-05

申请号：US15937937

申请日：2018-03-28

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US10223003B2

公开(公告)日：2019-03-05

申请号：US15807720

申请日：2017-11-09

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/42 ,  G11C5/06 ,  G11C8/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

公开(公告)号：US20150095733A1

公开(公告)日：2015-04-02

申请号：US14478824

申请日：2014-09-05

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hong Beom Pyeon ,  Young-Goan Kim

IPC: G01R31/317 ,  G01R31/3181

CPC classification number: G01R31/31713 ,  G01R31/31701 ,  G01R31/31813 ,  G11C16/00 ,  G11C29/1201 ,  G11C29/56 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.

Abstract translation: 一种装置，包括彼此串联连接的多个装置，每个装置包括用于接收指示启用测试模式的测试使能信号的测试使能引脚和用于输出测试输出信号的测试输出引脚 测试模式和耦合到所述设备的控制器，并且包括用于输出测试通道输出信号的附加测试输出引脚，其中所述测试输出信号和测试通道输出信号中的至少一个的故障指示存在一个或多个 与多个设备和控制器相关联的潜在缺陷。

公开(公告)号：US10679695B2

公开(公告)日：2020-06-09

申请号：US16249482

申请日：2019-01-16

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C7/10 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/06

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09977731B2

公开(公告)日：2018-05-22

申请号：US14027858

申请日：2013-09-16

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

IPC: G06F13/00 ,  G06F12/02 ,  G11C7/10 ,  G06F13/36 ,  G06F13/42 ,  G06F12/04 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

公开(公告)号：US09966133B2

公开(公告)日：2018-05-08

申请号：US15692206

申请日：2017-08-31

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/34 ,  G11C16/16 ,  G06F1/12 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09524783B2

公开(公告)日：2016-12-20

申请号：US14984303

申请日：2015-12-30

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Hakjune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。