公开(公告)号：US06251787B1

公开(公告)日：2001-06-26

申请号：US09514867

申请日：2000-02-28

申请人： Daniel C. Edelstein ,  Wilma J. Horkans ,  Stephen E. Luce ,  Naftall E. Lustig ,  Keith R. Pope ,  Peter D. Roper

发明人： Daniel C. Edelstein ,  Wilma J. Horkans ,  Stephen E. Luce ,  Naftall E. Lustig ,  Keith R. Pope ,  Peter D. Roper

IPC分类号： H01L2100

CPC分类号： B24B37/34 ,  B24B49/12 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67028

摘要： Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.

摘要翻译： 消除PN结对能够引起光伏效应的光和/或抑制由光电效应引起的氧化和还原反应的光的暴露防止金属组分通过电解电化学溶解在半导体器件上。 用于晶圆CMP，刷子清洁，卸载和冲洗的工具的变暗外壳将消除曝光。 或者，可以将半导体晶片的照明限制在不能提供足够能量以引起光伏效应的光的波长。 CMP浆料中的抑制剂和/或CMP后的水冲洗阻止氧化和/或还原反应。 封闭剂，例如高分子量表面活性剂，将干扰金属表面的氧化和还原反应。 此外，中毒剂会阻碍电解还原部分。

公开(公告)号：US6153043A

公开(公告)日：2000-11-28

申请号：US20010

申请日：1998-02-06

申请人： Daniel C. Edelstein ,  Wilma J. Horkans ,  Stephen E. Luce ,  Naftali E. Lustig ,  Keith R. Pope ,  Peter D. Roper

发明人： Daniel C. Edelstein ,  Wilma J. Horkans ,  Stephen E. Luce ,  Naftali E. Lustig ,  Keith R. Pope ,  Peter D. Roper

IPC分类号： H01L21/304 ,  B24B37/34 ,  B24B49/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/321 ,  C23F1/02

CPC分类号： B24B37/34 ,  B24B49/12 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/67028

摘要： Eliminating exposure of PN junctions to light capable of invoking a photovoltaic effect and/or inhibiting the oxidation and reduction reactions induced by the photovoltaic effect prevents the electrochemical dissolution of metal components on semiconductor devices by electrolysis. A darkened enclosure for use on tools for wafer CMP, brush cleaning, unloading, and rinsing will eliminate exposure. Alternatively, illumination of a semiconductor wafer can be limited to wavelengths of light that do not provide enough energy to induce a photovoltaic effect. An inhibitor in the CMP slurry and/or post-CMP water rinse blocks the oxidation and/or reduction reactions. A blocking agent, such as a high molecular weight surfactant, will interfere with both the oxidation and reduction reactions at the metal surface. Also, a poisoning agent will impede the reduction portion of electrolysis.

摘要翻译： 消除PN结对能够引起光伏效应的光和/或抑制由光电效应引起的氧化和还原反应的光的暴露防止金属组分通过电解电化学溶解在半导体器件上。 用于晶圆CMP，刷子清洁，卸载和冲洗的工具的变暗外壳将消除曝光。 或者，可以将半导体晶片的照明限制在不能提供足够能量以引起光伏效应的光的波长。 CMP浆料中的抑制剂和/或CMP后的水冲洗阻止氧化和/或还原反应。 封闭剂，例如高分子量表面活性剂，将干扰金属表面的氧化和还原反应。 此外，中毒剂会阻碍电解还原部分。

公开(公告)号：US09245794B2

公开(公告)日：2016-01-26

申请号：US13614492

申请日：2012-09-13

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Takeshi Nogami

IPC分类号： H05K1/09 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L21/76844 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

摘要翻译： 提供了包括直接位于扩散阻挡层和Cu合金种子层之间的合金衬垫的互连结构以及用于形成这种互连结构的方法。 本发明的合金衬垫通过使预先沉积的扩散阻挡金属合金层与覆盖的Cu合金种子层热反应形成。 在热反应期间，来自扩散阻挡层和Cu合金种子层的金属合金在扩散阻挡层和Cu籽晶层之间反应形成金属合金反应产物。

公开(公告)号：US09059251B2

公开(公告)日：2015-06-16

申请号：US13614524

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US08765602B2

公开(公告)日：2014-07-01

申请号：US13599256

申请日：2012-08-30

申请人： Thomas W. Dyer ,  Daniel C. Edelstein ,  Tze-man Ko ,  Andrew H. Simon ,  Wei-tsu Tseng

发明人： Thomas W. Dyer ,  Daniel C. Edelstein ,  Tze-man Ko ,  Andrew H. Simon ,  Wei-tsu Tseng

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer.

摘要翻译： 形成金属互连结构的方法包括在层间电介质（ILD）层内形成铜线; 用铜合金材料直接掺杂铜线的顶面; 并在ILD层和铜合金材料上形成介电层; 其中所述铜合金材料用于所述铜线和所述电介质层之间的粘合界面层。

公开(公告)号：US20140061915A1

公开(公告)日：2014-03-06

申请号：US13599295

申请日：2012-08-30

申请人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

发明人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76873 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

摘要翻译： 形成集成电路器件的方法包括在限定在衬底中的开口中形成扩散阻挡层; 在所述扩散阻挡层上形成高掺杂的铜合金种子层，所述铜合金种子层具有浓度大于0.5％原子的少数合金成分; 以及在所述铜合金晶种层上形成铜层，以限定所述集成电路器件的布线结构。

公开(公告)号：US20140024146A1

公开(公告)日：2014-01-23

申请号：US13565848

申请日：2012-08-03

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

公开(公告)号：US08564132B2

公开(公告)日：2013-10-22

申请号：US13211722

申请日：2011-08-17

申请人： Chih-Chao Yang ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Daniel C. Edelstein

IPC分类号： H01L23/482

CPC分类号： H01L21/76838 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76895

摘要： A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

摘要翻译： 提供局部互连结构，其中形成在中间线（MOL）电介质材料内的钨区域，即钨柱，在多重互连图案化工艺期间不被损坏和/或污染。 这在本公开内容中通过在顶部表面内形成自对准的氮化钨钝化层，并且在钨区域的上侧壁部分之上延伸到包括形成在其中的第一互连图案的MOL介电材料之上。 在自对准氮化钨钝化层的形成过程中，还会在MOL介电材料的暴露表面内形成富含氮的电介质表面。 然后形成与第一互连图案相邻但不连接的第二布线图案。 由于在钨区域上存在自对准的氮化钨钝化层，不会发生钨区域的破坏和/或污染。

公开(公告)号：US08497580B2

公开(公告)日：2013-07-30

申请号：US13191090

申请日：2011-07-26

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Fenton R. McFeely

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76826 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

摘要翻译： 提供了包括具有约3.0或更小介电常数的介电材料的互连结构。 该低k电介质材料具有至少一个具有嵌入其中的上表面的导电材料。 电介质材料还具有在形成贵金属盖之前被制成疏水性的表面层。 贵金属盖直接位于至少一个导电材料的上表面上。 由于在电介质材料上存在疏水表面层，贵金属盖基本上不会延伸到与至少一种导电材料相邻的电介质材料的疏水表面层上，并且没有贵金属帽的金属残留物 沉积形式在该疏水电介质表面上。

公开(公告)号：US08492289B2

公开(公告)日：2013-07-23

申请号：US12882500

申请日：2010-09-15

申请人： Daniel C. Edelstein ,  Takeshi Nogami ,  Hosadurga K. Shobha

发明人： Daniel C. Edelstein ,  Takeshi Nogami ,  Hosadurga K. Shobha

IPC分类号： H01L21/31

CPC分类号： H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.

摘要翻译： 形成用于集成电路器件的金属互连的势垒层的方法包括在集成电路器件的导电线的顶表面之上形成第一帽层，以便于提供给顶部表面的氧的可控剂量 所述导电线包括在作为所述金属的杂质合金的种子层上形成的金属; 以及对所述集成电路器件进行退火以将所述种子层的扩散杂质原子与可控量的氧组合，从而在所述第一覆盖层和所述导电线的顶表面之间的界面处形成杂质氧化物层。