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28 条记录 (耗时 0.031 秒)

    Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode
    2.
    发明申请
    Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode 有权
    金属绝缘体金属（MIM）电容器制造与侧壁间隔和铝帽（ALCAP）顶部电极

    公开(公告)号：US20060024899A1

    公开(公告)日：2006-02-02

    申请号：US10909648

    申请日：2004-07-31

    申请人： Darius Crenshaw ,  Byron Williams ,  Alwin Tsao ,  Hisashi Shichijo ,  Satyavolu Papa Rao ,  Kenneth Brennan ,  Steven Lytle

    发明人： Darius Crenshaw ,  Byron Williams ,  Alwin Tsao ,  Hisashi Shichijo ,  Satyavolu Papa Rao ,  Kenneth Brennan ,  Steven Lytle

    IPC分类号： H01L21/8242 ,  H01L21/20

    CPC分类号： H01L23/5223 ,  H01L21/76834 ,  H01L28/57 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

    摘要翻译： 公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。 侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些 边缘（153）的顶层电极材料层。 侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。 底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

    Integrated structure for reduced leakage and improved fill-factor in CMOS pixel
    3.
    发明授权
    Integrated structure for reduced leakage and improved fill-factor in CMOS pixel 有权
    集成结构，可减少泄漏，改善CMOS像素的填充因子

    公开(公告)号：US06392263B1

    公开(公告)日：2002-05-21

    申请号：US09855251

    申请日：2001-05-15

    申请人： Zhiliang J. Chen ,  Kuok Y. Ling ,  Hisashi Shichijo ,  Katsuo Komatsuzaki ,  Chin-Yu Tsai

    发明人： Zhiliang J. Chen ,  Kuok Y. Ling ,  Hisashi Shichijo ,  Katsuo Komatsuzaki ,  Chin-Yu Tsai

    IPC分类号： H01L2972

    CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/1463

    摘要： A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.

    摘要翻译： 由CMOS技术制造的密集集成的像素包括由n阱形成的光电二极管，阴极由p阱包围; 复位MOS晶体管形成为使得其多晶硅栅极被定位用于二极管控制，跨越由p阱和n阱区域形成的结，并且其源极与光电二极管阴极合并; 以及形成为使得其源极与复位晶体管的漏极组合的感测MOS晶体管，并且其栅极电连接到复位晶体管的源极。在本发明的像素中，光电二极管的漏电流大大降低，因为没有 n + / p-阱结连接到光电二极管，并且填充因子得到改善，因为像素尺寸大大降低。

    Integrated bipolar junction transistor for mixed signal circuits
    4.
    发明授权
    Integrated bipolar junction transistor for mixed signal circuits 有权
    用于混合信号电路的集成双极结型晶体管

    公开(公告)号：US06303420B1

    公开(公告)日：2001-10-16

    申请号：US09618413

    申请日：2000-07-18

    申请人： Seetharaman Sridhar ,  Amitava Chatterjee ,  Hisashi Shichijo ,  Alec J. Morton

    发明人： Seetharaman Sridhar ,  Amitava Chatterjee ,  Hisashi Shichijo ,  Alec J. Morton

    IPC分类号： H01L218238

    CPC分类号： H01L21/8249

    摘要： A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.

    摘要翻译： 一种用于形成用于混合信号电路的集成电路双极结型晶体管的方法。 用于形成CMOS电路20,40的阱区域的种植体形成双极结型晶体管的集电极区域。 CMOS晶体管插入口形成双极结型晶体管的基极区域，并且CMOS漏极延伸注入形成双极结型晶体管的发射极区域。

    PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT
    6.
    发明申请
    PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT 有权
    过程和温度敏感型闪烁噪声监测电路

    公开(公告)号：US20100197053A1

    公开(公告)日：2010-08-05

    申请号：US12761544

    申请日：2010-04-16

    申请人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

    发明人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

    IPC分类号： H01L21/66

    CPC分类号： H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

    摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

    摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字比特流与参考进行比较，以确定失败是否在允许的范围内。

    Multiple substrate bias random access memory device
    7.
    发明授权
    Multiple substrate bias random access memory device 失效
    多重衬底偏置随机存取存储器件

    公开(公告)号：US5894145A

    公开(公告)日：1999-04-13

    申请号：US909904

    申请日：1997-08-12

    申请人： Ih-Chin Chen ,  Hisashi Shichijo ,  Clarence W. Teng

    发明人： Ih-Chin Chen ,  Hisashi Shichijo ,  Clarence W. Teng

    IPC分类号： H01L21/8238 ,  H01L21/8226 ,  H01L21/8242 ,  H01L27/082 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

    CPC分类号： H01L27/10805 ,  H01L27/105

    摘要： A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

    摘要翻译： 动态随机存取存储器件（10）包括三个单独的部分 - 输入/输出部分（12），外围晶体管部分（14）和存储器阵列部分（16），全部形成在p型衬底层 18）。 动态随机存取存储器件（10）可以为每个部分采用单独的衬底偏置电压。 输入/输出部分（12）具有通过n-型阱区域（20）与p-型衬底层（18）隔离的p-型区域（22）。 外围晶体管部分（14）具有p型区域（36），其可以通过可选的n型阱区域（40）与p型衬底层（18）隔离，用于那些需要不同衬底偏置的器件 外围晶体管部分（14）和存储器阵列部分（16）之间的电压。

    MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS
    10.
    发明申请
    MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS 有权
    具有扩展孔的匹配模拟CMOS晶体管

    公开(公告)号：US20090140346A1

    公开(公告)日：2009-06-04

    申请号：US11948172

    申请日：2007-11-30

    申请人： Henry Litzmann Edwards ,  Hisashi Shichijo ,  Tathagata Chatterjee ,  Shyh-Horng Yang ,  Lance Stanford Robertson

    发明人： Henry Litzmann Edwards ,  Hisashi Shichijo ,  Tathagata Chatterjee ,  Shyh-Horng Yang ,  Lance Stanford Robertson

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L27/0928

    摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.

    摘要翻译： 本发明的一个实施例涉及集成电路。 集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸​​部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。 集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸​​部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。 模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。 还公开了其他装置，方法和系统。