公开(公告)号：US06638818B1

公开(公告)日：2003-10-28

申请号：US08726229

申请日：1996-10-04

申请人： Darius L. Crenshaw ,  Promod Kumar

发明人： Darius L. Crenshaw ,  Promod Kumar

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/88 ,  H01L28/90 ,  Y10S977/773 ,  Y10S977/888 ,  Y10S977/891 ,  Y10S977/943

摘要： A method for forming a dynamic random access memory with increased capacitance includes preparing (36) ultra-fine particles in a microemulsion. The particles are deposited (38) on the lower electrode layer of the memory cell. A micro-villus pattern is then formed (40) on the lower electrode layer, using the particles as a mask. A layer of HSG polysilicon may then be deposited (42) on the micro-villus pattern. A dielectric and upper electrode are then formed (44) overlying the lower electrode to form a storage capacitor for the dynamic random access memory.

摘要翻译： 用于形成具有增加的电容的动态随机存取存储器的方法包括制备（36）微乳液中的超细颗粒。 颗粒沉积（38）在存储单元的下电极层上。 然后使用该颗粒作为掩模，在下电极层上形成微绒毛图案（40）。 然后可以在微绒毛图案上沉积（42）HSG多晶硅层。 然后形成电介质和上电极（44），覆盖下电极以形成用于动态随机存取存储器的存储电容器。

公开(公告)号：US06698082B2

公开(公告)日：2004-03-02

申请号：US09941031

申请日：2001-08-28

申请人： Darius L. Crenshaw ,  Stuart M. Jacobsen ,  David J. Seymour

发明人： Darius L. Crenshaw ,  Stuart M. Jacobsen ,  David J. Seymour

IPC分类号： H01H4300

CPC分类号： H01H59/0009 ,  H01H1/0036 ,  Y10T29/435 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49117

摘要： The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

摘要翻译： 本发明提供了一种将电路中的偏置电阻与硅基板上的微机电开关的底电极集成的方法和方法。 电阻器和底部电极通过首先在形成叠层的硅衬底上依次沉积电阻材料层（320），硬掩模材料（330）和金属材料（340）而同时形成。 随后对底部电极和电阻器长度进行图案化和蚀刻（350），随后进行第二蚀刻（360）处理，以从限定的电阻器长度去除硬掩模和金属材料。 最后，在一个优选实施例中，底部电极和电阻器结构用一层电介质封装，电介质层被图案化并蚀刻（370）以对应于限定的底部电极和电阻器。

公开(公告)号：US06642593B2

公开(公告)日：2003-11-04

申请号：US09741128

申请日：2000-12-19

申请人： Tsen-Hwang Lin ,  Yu-Pei Chen ,  Darius L. Crenshaw

发明人： Tsen-Hwang Lin ,  Yu-Pei Chen ,  Darius L. Crenshaw

IPC分类号： H01L2982

CPC分类号： B81C1/00182 ,  B81B2201/018 ,  B81B2203/0118 ,  B81B2203/0127 ,  B81B2203/04 ,  H01G5/16 ,  H01G5/40 ,  H01H59/0009 ,  H01P1/127

摘要： A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

摘要翻译： 微机电开关包括衬底，从衬底向外设置的绝缘体层以及从绝缘体层向外设置的电极。 开关还包括从绝缘体层和电极向外设置的电介质层，电介质层的介电常数大于或等于二十。 所述开关还包括从所述电介质层向外设置的膜层，所述膜层覆盖在支撑层上，所述支撑层可操作以将所述膜层从所述电介质层向外空间。

公开(公告)号：US06699745B1

公开(公告)日：2004-03-02

申请号：US09049591

申请日：1998-03-27

申请人： Aditi Banerjee ,  Rick L. Wise ,  Darius L. Crenshaw

发明人： Aditi Banerjee ,  Rick L. Wise ,  Darius L. Crenshaw

IPC分类号： H01L218234

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/84 ,  Y10S438/964

摘要： A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

公开(公告)号：US5770499A

公开(公告)日：1998-06-23

申请号：US865577

申请日：1997-05-29

申请人： Siang Ping Kwok ,  Peter S. McAnally ,  Darius L. Crenshaw

发明人： Siang Ping Kwok ,  Peter S. McAnally ,  Darius L. Crenshaw

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/40

摘要： A planarized capacitor array (182) and method of forming the same for high density applications. A storage node contact (116) is formed through an interlevel dielectric (110) on a semiconductor body (102). Then, an oxide layer (170) having a first thickness is deposited over the interlevel dielectric (110) and the storage node contact (116). A nitride layer (172) having a second thickness is deposited over the oxide layer (170) to protect the oxide layer (170) during later processing. The nitride layer (172) and oxide layer (170) are then patterned and etched to form a storage plate cavity (180). The capacitor array (182) is then formed in the storage plate cavity (180). The capacitor array (182) has a height approximately equal to the sum of said first and second thicknesses, so that the surface of the top node of the capacitor array (182) is co-planar with the upper surface of the surrounding oxide/nitride stack (170/172). Thus, the step height normally present between the capacitor array (182) and the peripheral area is avoided.

摘要翻译： 平面化电容器阵列（182）及其形成方法，用于高密度应用。 存储节点触点（116）通过半导体本体（102）上的层间电介质（110）形成。 然后，具有第一厚度的氧化物层（170）沉积在层间电介质（110）和存储节点接触点（116）上。 具有第二厚度的氮化物层（172）沉积在氧化物层（170）上，以在后续处理期间保护氧化物层（170）。 然后对氮化物层（172）和氧化物层（170）进行图案化和蚀刻以形成存储板腔（180）。 然后，电容器阵列（182）形成在存储板空腔（180）中。 电容器阵列（182）具有大致等于所述第一和第二厚度之和的高度，使得电容器阵列（182）的顶部节点的表面与周围的氧化物/氮化物的上表面共面 堆栈（170/172）。 因此，避免了在电容器阵列（182）和外围区域之间通常存在的台阶高度。

公开(公告)号：US06496352B2

公开(公告)日：2002-12-17

申请号：US09335348

申请日：1999-06-17

申请人： Darius L. Crenshaw ,  William F. Richardson ,  Rick L. Wise

发明人： Darius L. Crenshaw ,  William F. Richardson ,  Rick L. Wise

IPC分类号： H01G4005

CPC分类号： H01L28/91 ,  H01L21/3212 ,  H01L28/84

摘要： A post-in-crown capacitor is disclosed. The post-in-crown capacitor (60) includes a crown (44) coupled to a conductive via (20). A post (48) is disposed within the crown (44) and a capacitor insulation layer (50) is formed outwardly from the crown (44) and the post (48). A capacitor plate layer (52) is then formed outwardly from the capacitor insulation layer (50).

摘要翻译： 公开了一种后置电容器。 冠状后电容器（60）包括联接到导电通路（20）的表冠（44）。 柱（48）设置在表冠（44）内，并且从表冠（44）和柱（48）向外形成电容器绝缘层（50）。 然后从电容器绝缘层（50）向外形成电容器板层（52）。

公开(公告)号：US06376787B1

公开(公告)日：2002-04-23

申请号：US09648288

申请日：2000-08-24

申请人： Wallace W. Martin ,  Yu-Pei Chen ,  Byron Williams ,  Jose Melendez ,  Darius L. Crenshaw

发明人： Wallace W. Martin ,  Yu-Pei Chen ,  Byron Williams ,  Jose Melendez ,  Darius L. Crenshaw

IPC分类号： H01H5700

CPC分类号： H01H59/0009 ,  G11C23/00 ,  H01G5/16 ,  H01G5/40 ,  H01H2001/0084 ,  H01P1/127 ,  Y10T29/49105

摘要： A Micro Electro-Mechanical System (MEMS) switch (100) having a bottom electrode (116) formed over a substrate (112) and a thin protective cap layer (130) disposed over the bottom electrode (116). A dielectric material (118) is disposed over the protective cap layer (130) and a pull-down electrode (122) is formed over the spacer (120) and the dielectric material (118). The protective cap layer (130) prevents the oxidation of the bottom electrode (116). The thin protective cap layer (130) comprises a metal having an associated oxide with a high dielectric constant. A portion (132) of the thin protective cap layer (130) may oxidize during the formation of the dielectric material (118), increasing the capacitance of the dielectric stack (128).

摘要翻译： 具有形成在衬底（112）上的底部电极（116）的微机电系统（MEMS）开关（100）和设置在底部电极（116）上方的薄的保护盖层（130）。 电介质材料（118）设置在保护盖层（130）上方，并且在间隔物（120）和电介质材料（118）之上形成下拉电极（122）。 保护盖层（130）防止底部电极（116）的氧化。 薄保护盖层（130）包括具有高介电常数的相关氧化物的金属。 在形成电介质材料（118）期间，薄保护盖层（130）的一部分（132）可能会氧化，从而增加电介质堆叠（128）的电容。

公开(公告)号：US07250334B2

公开(公告)日：2007-07-31

申请号：US10909648

申请日：2004-07-31

申请人： Darius L. Crenshaw ,  Byron L. Williams ,  Alwin Tsao ,  Hisashi Shichijo ,  Satyavolu S. Papa Rao ,  Kenneth D. Brennan ,  Steven A. Lytle

发明人： Darius L. Crenshaw ,  Byron L. Williams ,  Alwin Tsao ,  Hisashi Shichijo ,  Satyavolu S. Papa Rao ,  Kenneth D. Brennan ,  Steven A. Lytle

IPC分类号： H01L21/8242

CPC分类号： H01L23/5223 ,  H01L21/76834 ,  H01L28/57 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

摘要翻译： 公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。 侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些 边缘（153）的顶层电极材料层。 侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。 底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

公开(公告)号：US07115467B2

公开(公告)日：2006-10-03

申请号：US10903712

申请日：2004-07-30

申请人： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

发明人： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

IPC分类号： H01L21/8242

CPC分类号： H01L28/75

摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).

公开(公告)号：US06977196B1

公开(公告)日：2005-12-20

申请号：US10642969

申请日：2003-08-18

申请人： Darius L. Crenshaw ,  Stuart M. Jacobsen ,  David J. Seymour

发明人： Darius L. Crenshaw ,  Stuart M. Jacobsen ,  David J. Seymour

IPC分类号： H01C7/00 ,  H01H1/00 ,  H01H59/00 ,  H01L21/822 ,  H01L27/04 ,  H01P1/10 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01H59/0009 ,  H01H1/0036 ,  Y10T29/435 ,  Y10T29/49004 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49117

摘要： The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.

摘要翻译： 本发明提供了一种将电路中的偏置电阻与硅基板上的微机电开关的底电极集成的方法和方法。 电阻器和底部电极通过首先在形成叠层的硅衬底上依次沉积电阻材料层（320），硬掩模材料（330）和金属材料（340）而同时形成。 随后对底部电极和电阻器长度进行图案化和蚀刻（350），随后进行第二蚀刻（360）处理，以从限定的电阻器长度去除硬掩模和金属材料。 最后，在一个优选实施例中，底部电极和电阻器结构用一层电介质封装，电介质层被图案化并蚀刻（370）以对应于限定的底部电极和电阻器。