公开(公告)号：US06319828B1

公开(公告)日：2001-11-20

申请号：US09317537

申请日：1999-05-24

申请人： Do Soo Jeong ,  Hai Jeong Sohn ,  Dong Ho Lee

发明人： Do Soo Jeong ,  Hai Jeong Sohn ,  Dong Ho Lee

IPC分类号： H01L2144

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for manufacturing a chip scale package comprises preparing a tape wiring board that includes a polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the tape, a window formed in the tape to enable the Cu traces to be connected to a semiconductor chip attached below the board, multiple connection holes formed in the tape to expose portions of the Cu traces therethrough and define solder ball mounting pads, and an elastomer chip carrier attached to the bottom surface of the tape. The method includes applying either a pre-flux or a cover sheet over the solder ball mounting pads. The pre-flux and the cover sheet each prevents the solder ball mounting pads being plated with gold. This, in turn, prevents the formation of intermetallic compounds in the solder balls so that the bond strength between the solder balls and a pad to which they attach is improved.

摘要翻译： 一种芯片级封装的制造方法包括：制备带布线板，其包括具有顶表面和底表面的聚酰亚胺带，形成在带的底表面上的Cu迹线，形成在带中的窗口，以使铜迹线能够连接 连接到板下方的半导体芯片，形成在带中的多个连接孔以暴露Cu迹线的部分以及限定焊球安装焊盘，以及附接到带的底表面的弹性体芯片载体。 该方法包括在焊球安装焊盘上施加预通量或覆盖片。 预焊剂和覆盖片各自防止焊球安装垫被镀金。 这反过来又防止了焊料球中的金属间化合物的形成，从而提高了焊料球与其附着的焊盘之间的结合强度。

公开(公告)号：US5811875A

公开(公告)日：1998-09-22

申请号：US673278

申请日：1996-06-28

申请人： Do Soo Jeong ,  Hai Jeong Sohn ,  Hyeon Jo Jeong

发明人： Do Soo Jeong ,  Hai Jeong Sohn ,  Hyeon Jo Jeong

IPC分类号： H01L23/495 ,  H01L23/28 ,  H01L23/48 ,  H01L23/50 ,  H01L29/44

CPC分类号： H01L23/4951 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L24/48 ,  H01L2924/00014

摘要： Lead frames for semiconductor chips include spaced apart tie-bars which extend to contact and support the semiconductor chip. Adhesive is used between the tie-bars and the chip to adhesively couple the tie-bars to the chip. The lead frame leads therefore need not be used to adhesively couple the chip to the lead frame, thereby reducing or eliminating the need for equal spacing and close coupling of the leads, and reducing or preventing problems caused by deterioration of adhesive on the leads. The tie-bars may include polyimide tape or liquid adhesive held in cups. During fabrication, a semiconductor chip is mounted on the adhesive material, such that the tie-bars mechanically support the semiconductor chip and the lead ends extend adjacent the semiconductor chip. The lead ends are then electrically connected to the semiconductor chip and the package is encapsulated.

摘要翻译： 用于半导体芯片的引线框架包括间隔开的连接杆，其延伸以接触和支撑半导体芯片。 在连杆和芯片之间使用粘合剂将连接杆粘合到芯片上。 因此，引线框架引线不需要用于将芯片粘合到引线框架上，从而减少或消除对引线的相等间隔和紧密耦合的需要，并且减少或防止由引线上的粘合剂劣化引起的问题。 连接杆可以包括保持在杯中的聚酰亚胺胶带或液体粘合剂。 在制造期间，半导体芯片安装在粘合剂材料上，使得连接杆机械地支撑半导体芯片，并且引线端部延伸到相邻的半导体芯片。 然后引线端电连接到半导体芯片，封装封装。

公开(公告)号：US6013946A

公开(公告)日：2000-01-11

申请号：US831465

申请日：1997-03-31

申请人： Kyu Jin Lee ,  Do Soo Jeong ,  Jae June Kim

发明人： Kyu Jin Lee ,  Do Soo Jeong ,  Jae June Kim

IPC分类号： H01L23/28 ,  H01L21/50 ,  H01L23/02 ,  H01L23/04 ,  H01L23/10 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/06 ,  H01L23/495

CPC分类号： H01L23/13 ,  H01L21/50 ,  H01L23/10 ,  H01L23/24 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/30107

摘要： A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace. Furthermore, the input/output pads can be on an interior portion of the surface of the semiconductor chip, and the insulating layer can have an opening therein for exposing the input/output pads. Accordingly, a dam on the second surface of the insulating layer can be provided around the opening wherein each of the conductive traces extends from adjacent the opening under the dam to a portion of the insulating layer outside the dam. Related methods and assemblies are also discussed.

摘要翻译： 包括多个输入/输出焊盘的半导体芯片的封装包括绝缘层和多个导电迹线。 绝缘层具有用于与半导体芯片的表面接合的第一表面，使得输入/输出焊盘在绝缘层附近露出。 导电迹线设置在与第一表面相对的绝缘层的第二表面上，其中每个导电迹线对应于输入/输出焊盘中的相应一个。 特别地，导电迹线适于接收多个接合线，每个接合线对应于相应的一个输入/输出焊盘。 因此，每个接合线可以在第一端处接合到相应的输入/输出焊盘，并且在第二端可以接合到相应的导电迹线。 此外，输入/输出焊盘可以在半导体芯片的表面的内部，并且绝缘层可以具有用于暴露输入/输出焊盘的开口。 因此，可以在开口周围设置绝缘层的第二表面上的堤坝，其中每个导电迹线从坝的下方的开口附近延伸到坝外部的绝缘层的一部分。 还讨论了相关方法和装配。

公开(公告)号：US5744827A

公开(公告)日：1998-04-28

申请号：US753532

申请日：1996-11-26

申请人： Do Soo Jeong ,  Min Cheol An ,  Seung Ho Ahn ,  Hyeon Jo Jeong ,  Ki Won Choi

发明人： Do Soo Jeong ,  Min Cheol An ,  Seung Ho Ahn ,  Hyeon Jo Jeong ,  Ki Won Choi

IPC分类号： H01L25/18 ,  H01L23/28 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L25/11 ,  H01L27/00 ,  H01L23/48 ,  H01L23/02 ,  H01L25/04

CPC分类号： H01L23/49551 ,  H01L23/4951 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511

摘要： A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps. The three dimensional package device includes a plurality of individual semiconductor devices, each individual semiconductor device including (1) a semiconductor chip, (2) a protective body for encapsulating the semiconductor chip, (3) a lead frame comprising inner lead portions electrically interconnected to the semiconductor chip and included within the protective body, outer lead portions formed as a single body with the inner lead portions, and coupling lead portions located between the inner and outer lead portions and having a top surface exposed upward from the protective body, and (4) a plurality of vertical interconnection elements attached to a back surface of the coupling lead portions and exposed from the protective body in a direction opposing the exposed top surface of the coupling lead portions, whereby, an electrical interconnection of the plurality of individual semiconductor devices is accomplished by the coupling lead portions and the vertical interconnection elements, and electrical interconnection of the three dimensional stack package device to an external circuit device is accomplished by the outer lead portions of a lowermost semiconductor device.

摘要翻译： 一种三维堆叠封装装置，可以实现堆叠的单个封装装置的垂直电互连，而无需成本增加或额外复杂的处理步骤。 三维封装器件包括多个单独的半导体器件，每个单独的半导体器件包括（1）半导体芯片，（2）用于封装半导体芯片的保护体，（3）引线框架，其包括内部引线部分， 所述半导体芯片包括在所述保护体内，所述外部引线部分与所述内部引线部分形成为单一主体，以及耦合引线部分，位于所述内引线部分和所述引线部分之间，并且具有从所述保护体向上露出的顶表面，以及 4）多个垂直互连元件，其附接到所述耦合引线部分的后表面并且从与所述耦合引线部分的暴露的顶表面相对的方向从所述保护体露出，由此所述多个单独的半导体器件 由耦合引线部分和垂直互连元件实现 并且三维堆叠封装器件与外部电路器件的电互连由最下半导体器件的外部引线部分实现。

公开(公告)号：US6087722A

公开(公告)日：2000-07-11

申请号：US291913

申请日：1999-04-14

申请人： Kwan Jai Lee ,  Young Jae Song ,  Do Soo Jeong ,  Tae Je Cho ,  Suk Hong Chang ,  Chang Cheol Lee ,  Beung Seuck Song ,  Jong Hee Choi

发明人： Kwan Jai Lee ,  Young Jae Song ,  Do Soo Jeong ,  Tae Je Cho ,  Suk Hong Chang ,  Chang Cheol Lee ,  Beung Seuck Song ,  Jong Hee Choi

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L23/48

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181

摘要： A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips. The auxiliary leads can also be positioned to prevent undesirable spreading of an adhesive when an upper chip is attached to a lower chip.

摘要翻译： 多芯片堆叠封装不包括管芯焊盘。 消除管芯垫为封装中的元件提供了更多的空间。 因此，可以实现平衡的内包装结构，并且可以避免可能暴露包装元件之一的不良成型。 在封装中，上芯片结合到下芯片的顶表面。 为了稳定芯片，引线框架的辅助引线或内引线连接到下芯片的顶表面。 这缩短了芯片和内部引线之间的电线长度。 较短的电线可以降低电线回路高度，从而降低在随后的传递模塑中暴露电线的可能性。 还公开了一种包括辅助引线的多芯片堆叠封装。 辅助引线连接到下芯片的顶表面，并且可以提供半导体芯片的稳定支撑，并防止芯片在传递成型中倾斜和移位。 辅助引线可以在下部和上部芯片之间。 辅助引线也可以被定位以防止当上芯片附接到下芯片时粘合剂的不希望的扩散。

公开(公告)号：US5894107A

公开(公告)日：1999-04-13

申请号：US904756

申请日：1997-08-01

申请人： Kyu Jin Lee ,  Do Soo Jeong ,  Wan Gyan Choi ,  Tae Gyeong Chung

发明人： Kyu Jin Lee ,  Do Soo Jeong ,  Wan Gyan Choi ,  Tae Gyeong Chung

IPC分类号： H01L23/50 ,  H01L23/48 ,  H01L23/495 ,  H01L23/28

CPC分类号： H01L23/4951 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/30107

摘要： A method for manufacturing a chip-size package and the chip-size package produced by the method uses first and second lead frames which are prepared by a stamping process. The first lead frame has leads with receiving parts, and the leads are integrally formed with lengthwise side rails of the lead frame. The second lead frame has external connections which align with the receiving parts of the leads when the second lead frame is positioned on top of the first lead frame and attached thereto. Guide holes located on the crosswise side rails of both lead frames can be used to easily align the two lead frames. A semiconductor chip is then adhered to the underside of the first lead frame, and the bonding pads of the semiconductor chip are electrically connected to the leads of the first lead frame. Then the two lead frames and the chip are encapsulated, with only the external connections of the second lead frame remaining exposed to the outside. Solder balls are then attached to the external connections for mounting onto a substrate. This chip-size package is inexpensive to produce, because the first and second lead frames can be produced by a stamping process, which is less complex and cheaper than the conventional half-etching process.

摘要翻译： 制造芯片尺寸封装的方法和通过该方法制造的芯片尺寸封装使用通过冲压工艺制备的第一和第二引线框架。 第一引线框架具有带有接收部件的引线，并且引线与引线框架的纵向侧轨整体形成。 当第二引线框架位于第一引线框架的顶部并附接到其上时，第二引线框架具有与引线的接收部分对准的外部连接。 可以使用位于两个引线框架的横向侧轨上的导向孔来容易地对准两个引线框架。 然后将半导体芯片粘附到第一引线框架的下侧，并且半导体芯片的焊盘电连接到第一引线框架的引线。 然后，两个引线框架和芯片被封装，只有第二引线框架的外部连接保持暴露于外部。 然后将焊球连接到外部连接以安装到基板上。 这种芯片尺寸的封装是便宜的，因为第一和第二引线框架可以通过冲压工艺生产，该冲压工艺比传统的半蚀刻工艺不那么复杂和便宜。

公开(公告)号：US06229205B1

公开(公告)日：2001-05-08

申请号：US09081566

申请日：1998-05-19

申请人： Do Soo Jeong ,  Kyung Seob Kim

发明人： Do Soo Jeong ,  Kyung Seob Kim

IPC分类号： H01L23495

CPC分类号： H01L23/49551 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

摘要： A semiconductor device package includes a die pad to which a semiconductor chip is vertically attached, having a smaller horizontal size than a horizontal size of the semiconductor chip. The package includes a plurality of inner leads which are electrically connected to the semiconductor chip, a plurality of outer leads each of which is integral with a respective one of the plurality of inner leads, a tie bar, and a package body for encapsulating the semiconductor chip, the die pad, and the plurality of inner leads. The tie bar for supporting the die pad has a downward bend effecting a downward vertical displacement from the die pad, and has a laterally spaced apart upward bend effecting an upward vertical displacement from the die pad. This package prevents imperfect encapsulation and resulting problems such as cracking of the package, and reduces damage to the die pad, such as warping of the die pad.

摘要翻译： 半导体器件封装包括垂直安装半导体芯片的芯片焊盘，其尺寸比半导体芯片的水平尺寸小。 该封装包括电连接到半导体芯片的多个内部引线，多个外部引线，每个外部引线与多个内部引线中的相应一个内部引线成一体，连接杆和用于封装半导体的封装体 芯片，芯片焊盘和多个内部引线。 用于支撑管芯焊盘的连接杆具有向下弯曲，从而从管芯焊盘向下垂直移位，并且具有横向间隔开的向上弯曲，从而实现与管芯焊盘的向上垂直位移。 该封装防止了不完美的封装和产生的问题，例如封装的破裂，并且减少了裸片焊盘的损坏，例如管芯焊盘的翘曲。

公开(公告)号：US5804874A

公开(公告)日：1998-09-08

申请号：US811150

申请日：1997-03-04

申请人： Min Cheol An ,  Do Soo Jeong

发明人： Min Cheol An ,  Do Soo Jeong

IPC分类号： H01L25/18 ,  H01L23/04 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L24/83 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/181

摘要： A stacked chip package comprising an upper part including an upper semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; an upper lead frame having leads extending over the active surface of the upper semiconductor chip and which are electrically interconnected to the electrode bonding pads of the semiconductor chip; a lower part including a lower semiconductor chip having a plurality of electrode bonding pads disposed on a central region of an active surface of the semiconductor chip; a lower lead frame having inner leads extending over the active surface of the lower semiconductor chip which are electrically interconnected to the electrode bonding pads of the lower semiconductor chip, and outer leads for electrical interconnecting the stacked chip package to an external circuit device. The leads of the upper lead frame are formed to directly contact top surfaces of the inner leads of the lower lead frame, so that the upper and the lower parts can be electrically interconnected. An insulating adhesive film is interposed between the upper semiconductor chip and the inner leads of the lower lead frame.

摘要翻译： 一种堆叠式芯片封装，包括上部，其包括上半导体芯片，所述上半导体芯片具有设置在所述半导体芯片的有源表面的中心区域上的多个电极接合焊盘; 上引线框架，其具有在所述上半导体芯片的有源表面上延伸并且与所述半导体芯片的电极接合焊盘电互连的引线; 下部包括具有设置在半导体芯片的有源表面的中心区域上的多个电极接合焊盘的下半导体芯片; 下引线框架具有在下半导体芯片的有源表面上延伸的内引线，其电连接到下半导体芯片的电极接合焊盘，以及外引线，用于将堆叠的芯片封装电连接到外部电路器件。 上引线框架的引线形成为直接接触下引线框架的内引线的顶表面，使得上和下部件可以电互连。 在上半导体芯片和下引线框架的内引线之间插入绝缘粘合膜。