公开(公告)号：US06348076B1

公开(公告)日：2002-02-19

申请号：US09472961

申请日：1999-12-28

申请人： Donald F. Canaperi ,  William J. Cote ,  Paul Feeney ,  Mahadevaiyer Krishnan ,  Joyce C. Liu ,  Michael F. Lofaro ,  Philip Murphy ,  Eric Jeffrey White

发明人： Donald F. Canaperi ,  William J. Cote ,  Paul Feeney ,  Mahadevaiyer Krishnan ,  Joyce C. Liu ,  Michael F. Lofaro ,  Philip Murphy ,  Eric Jeffrey White

IPC分类号： C09G102

CPC分类号： C23F3/00 ,  C09G1/02 ,  H01L21/3212

摘要： Slurry compositions comprising an oxidizing agent, copper corrosion inhibitor, abrasive particles; surface active agent and polyelectrolyte are useful for polishing or planarizing chip interconnect/wiring material such as Al, W and especially Cu.

摘要翻译： 包含氧化剂，铜缓蚀剂，磨料颗粒的浆料组合物; 表面活性剂和聚电解质可用于抛光或平面化芯片互连/布线材料如Al，W，特别是Cu。

公开(公告)号：US06812193B2

公开(公告)日：2004-11-02

申请号：US10231047

申请日：2002-08-30

申请人： Michael Todd Brigham ,  Donald Francis Canaperi ,  Michael Addison Cobb ,  William Cote ,  Kenneth Morgan Davis ,  Scott Alan Estes ,  Edward Jack Gordon ,  James Willard Hannah ,  Mahadevaiyer Krishnan ,  Michael Francis Lofaro ,  Michael Joseph MacDonald ,  Dean Allen Schaffer ,  George James Slusser ,  James Anthony Tornello ,  Eric Jeffrey White

发明人： Michael Todd Brigham ,  Donald Francis Canaperi ,  Michael Addison Cobb ,  William Cote ,  Kenneth Morgan Davis ,  Scott Alan Estes ,  Edward Jack Gordon ,  James Willard Hannah ,  Mahadevaiyer Krishnan ,  Michael Francis Lofaro ,  Michael Joseph MacDonald ,  Dean Allen Schaffer ,  George James Slusser ,  James Anthony Tornello ,  Eric Jeffrey White

IPC分类号： C09K1300

CPC分类号： C11D3/046 ,  C11D7/34 ,  C11D11/0047 ,  H01L21/3212

摘要： Slurry compositions comprising an oxidizing agent, optionally a copper corrosion inhibitor, abrasive particles; surface active agent, a service of chloride and a source of sulfate ions.

摘要翻译： 包含氧化剂，任选的铜腐蚀抑制剂，磨料颗粒的浆料组合物; 表面活性剂，氯化物和硫酸根离子的使用。

公开(公告)号：US08236580B2

公开(公告)日：2012-08-07

申请号：US12973062

申请日：2010-12-20

申请人： Jay Sanford Burnham ,  Joseph Kerry Vaughn Comeau ,  Leslie Peter Crane ,  James Randall Elliott ,  Scott Alan Estes ,  James Spiros Nakos ,  Eric Jeffrey White

发明人： Jay Sanford Burnham ,  Joseph Kerry Vaughn Comeau ,  Leslie Peter Crane ,  James Randall Elliott ,  Scott Alan Estes ,  James Spiros Nakos ,  Eric Jeffrey White

IPC分类号： H01L21/00

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.

摘要翻译： 监测铜污染的方法。 该方法包括：（a）将N型掺杂剂离子注入到单晶硅衬底的区域中，所述区域邻接衬底的顶表面; （c）通过在惰性气氛中在500℃或更高的温度下对衬底退火来活化N型掺杂剂; （c）在一段时间内将基底浸入水溶液中，以监测铜污染的水溶液; 和（d）通过基底区域确定从水溶液中吸附的铜的量。

公开(公告)号：US07851353B2

公开(公告)日：2010-12-14

申请号：US12142870

申请日：2008-06-20

申请人： Felix Patrick Anderson ,  Zhong-Xiang He ,  Thomas Leddy McDevin ,  Eric Jeffrey White

发明人： Felix Patrick Anderson ,  Zhong-Xiang He ,  Thomas Leddy McDevin ,  Eric Jeffrey White

IPC分类号： H01L21/4763

CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L21/76886 ,  H01L23/5228 ,  H01L23/53271 ,  H01L28/24 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming metal silicide layers. The methods include: forming a silicon-rich layer between dielectric layers; contacting the silicon-rich layer with a metal layer and heating the silicon rich-layer and the metal layer to diffuse metal atoms from the metal layer into the silicon layer to form a metal silicide layer.

摘要翻译： 形成金属硅化物层的方法。 所述方法包括：在电介质层之间形成富硅层; 使富硅层与金属层接触并加热富硅层和金属层，以将金属原子从金属层扩散到硅层中以形成金属硅化物层。

公开(公告)号：US20090317972A1

公开(公告)日：2009-12-24

申请号：US12142870

申请日：2008-06-20

申请人： Felix Patrick Anderson ,  Zhong-Xiang He ,  Thomas Leddy McDevin ,  Eric Jeffrey White

发明人： Felix Patrick Anderson ,  Zhong-Xiang He ,  Thomas Leddy McDevin ,  Eric Jeffrey White

IPC分类号： H01L21/768

CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L21/76886 ,  H01L23/5228 ,  H01L23/53271 ,  H01L28/24 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming metal silicide layers. The methods include: forming a silicon-rich layer between dielectric layers; contacting the silicon-rich layer with a metal layer and heating the silicon rich-layer and the metal layer to diffuse metal atoms from the metal layer into the silicon layer to form a metal silicide layer.

摘要翻译： 形成金属硅化物层的方法。 所述方法包括：在电介质层之间形成富硅层; 使富硅层与金属层接触并加热富硅层和金属层，以将金属原子从金属层扩散到硅层中以形成金属硅化物层。

公开(公告)号：US5665655A

公开(公告)日：1997-09-09

申请号：US501908

申请日：1995-07-13

申请人： Eric Jeffrey White

发明人： Eric Jeffrey White

IPC分类号： H01L21/301 ,  H01L21/3205 ,  H01L23/00 ,  H01L23/52 ,  H01L21/304

CPC分类号： H01L23/562 ,  H01L2924/0002 ,  H01L2924/13091

摘要： A process for making a crackstop on a semiconductor device is disclosed. The process involves creating and metallizing a groove surrounding the active region on a chip at the same time as other functional metallization is occurring, and then selectively etching out the metal in the groove after final passivation. In various embodiments the groove passes through the surface dielectric or the semiconductor substrate. In one embodiment the groove is replaced by hollow metal rings that can be stacked through multiple dielectric layers.

摘要翻译： 公开了一种在半导体器件上制作裂缝的工艺。 该过程涉及在发生其它功能性金属化的同时在芯片上产生和金属化围绕有源区的沟槽，然后在最终钝化之后选择性地蚀刻凹槽中的金属。 在各种实施例中，凹槽通过表面电介质或半导体衬底。 在一个实施例中，凹槽由可以通过多个介电层堆叠的中空金属环代替。

公开(公告)号：US20090088984A1

公开(公告)日：2009-04-02

申请号：US11863623

申请日：2007-09-28

申请人： Jay Sanford Burnham ,  Joseph Kerry Vaughn Comeau ,  Leslie Peter Crane ,  James Randall Elliott ,  Scott Alan Estes ,  James Spiros Nakos ,  Eric Jeffrey White

发明人： Jay Sanford Burnham ,  Joseph Kerry Vaughn Comeau ,  Leslie Peter Crane ,  James Randall Elliott ,  Scott Alan Estes ,  James Spiros Nakos ,  Eric Jeffrey White

IPC分类号： G01N33/00 ,  G06F19/00

CPC分类号： G01N33/1813 ,  H01L22/12 ,  H01L22/20

摘要： A computer system. The computer system including a processor and memory unit coupled to the processor, the memory unit containing instructions that when executed by the processor implement a method for monitoring a solution in a tank used to fabricate integrated circuits, the method comprising the computer implemented steps of: (a) collecting data indicating of an amount of copper in a region of a substrate of a monitor, the monitor comprising an N-type region in a silicon substrate, the region abutting a top surface of the substrate, the monitor having been submerged in the solution for a preset time; (b) comparing the data to a specification for copper content of the solution; (c) if the data indicates a copper content exceeds a limit of the specification for copper, indicating a corrective action is required to prevent copper contamination of the integrated circuits; and (d) repeating steps (a) through (c) periodically.

摘要翻译： 电脑系统 所述计算机系统包括处理器和耦合到所述处理器的存储器单元，所述存储器单元包含当由所述处理器执行时执行用于监视用于制造集成电路的箱中的解决方案的方法的指令，所述方法包括所述计算机实现的步骤： （a）收集指示在监视器的基板的区域中的铜量的数据，所述监视器包括在硅衬底中的N型区域，所述区域邻接所述衬底的顶表面，所述监视器已经被浸没在 解决方案预设时间; （b）将数据与解决方案中铜含量的规格进行比较; （c）如果数据表明铜含量超过铜规格的限制，则表明需要采取纠正措施以防止集成电路的铜污染; 和（d）定期重复步骤（a）至（c）。

公开(公告)号：US06394638B1

公开(公告)日：2002-05-28

申请号：US09560212

申请日：2000-04-28

申请人： Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

发明人： Edward W. Sengle ,  Mark D. Jaffe ,  Daniel Nelson Maynard ,  Mark Alan Lavin ,  Eric Jeffrey White ,  John A. Bracchitta

IPC分类号： H01L21762

CPC分类号： H01L21/76224 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

摘要翻译： 提供了一种用于半导体的沟槽隔离结构，包括隔离环和隔离路径。 隔离环围绕有源半导体区域，并且在非活性半导体区域的外部界定。 隔离通道从隔离环延伸穿过非活性半导体区域。 隔离路径上的第一级导体将有源半导体区域中的器件电连接或电容耦合到隔离环外部的衬底上的位置。 隔离路径具有从导体的布局导出的配置。

公开(公告)号：US20110086442A1

公开(公告)日：2011-04-14

申请号：US12973062

申请日：2010-12-20

申请人： Jay Sanford Burnham ,  Joseph Kerry Vaughn Comeau ,  Leslie Peter Crane ,  James Randall Elliott ,  Scott Alan Estes ,  James Spiros Nakos ,  Eric Jeffrey White

发明人： Jay Sanford Burnham ,  Joseph Kerry Vaughn Comeau ,  Leslie Peter Crane ,  James Randall Elliott ,  Scott Alan Estes ,  James Spiros Nakos ,  Eric Jeffrey White

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L22/12

摘要： A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.

摘要翻译： 监测铜污染的方法。 该方法包括：（a）将N型掺杂剂离子注入到单晶硅衬底的区域中，所述区域邻接衬底的顶表面; （c）通过在惰性气氛中在500℃或更高的温度下对衬底退火来活化N型掺杂剂; （c）在一段时间内将基底浸入水溶液中，以监测铜污染的水溶液; 和（d）通过基底区域确定从水溶液中吸附的铜的量。

公开(公告)号：US07245025B2

公开(公告)日：2007-07-17

申请号：US11164653

申请日：2005-11-30

申请人： Jeffrey Alan Brigante ,  Zhong-Xiang He ,  Barbara Ann Waterhouse ,  Eric Jeffrey White

发明人： Jeffrey Alan Brigante ,  Zhong-Xiang He ,  Barbara Ann Waterhouse ,  Eric Jeffrey White

IPC分类号： H01L23/48

CPC分类号： H01L23/53214 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.

摘要翻译： 一种形成结构的结构和方法。 该结构包括：集成电路芯片，其具有从第一布线级别到最后布线级别的布线级别的集合，每个布线级别包括嵌入在相应的层间电介质层中的一个或多个镶嵌，双镶嵌线或镶嵌孔，顶部 最后一个镶嵌层或最后布线层的双镶嵌线的表面与相应的最后层间介电层的顶表面基本共面; 与最后的镶嵌或双镶嵌线的顶表面直接物理和电接触的封盖层，包括铜的最后镶嵌或双镶嵌线; 形成在最后层间电介质层的顶表面上的电介质钝化层; 以及与覆盖层直接物理和电接触的铝焊盘，铝焊盘的顶表面未被电介质钝化层覆盖。