公开(公告)号：US06348076B1

公开(公告)日：2002-02-19

申请号：US09472961

申请日：1999-12-28

申请人： Donald F. Canaperi ,  William J. Cote ,  Paul Feeney ,  Mahadevaiyer Krishnan ,  Joyce C. Liu ,  Michael F. Lofaro ,  Philip Murphy ,  Eric Jeffrey White

发明人： Donald F. Canaperi ,  William J. Cote ,  Paul Feeney ,  Mahadevaiyer Krishnan ,  Joyce C. Liu ,  Michael F. Lofaro ,  Philip Murphy ,  Eric Jeffrey White

IPC分类号： C09G102

CPC分类号： C23F3/00 ,  C09G1/02 ,  H01L21/3212

摘要： Slurry compositions comprising an oxidizing agent, copper corrosion inhibitor, abrasive particles; surface active agent and polyelectrolyte are useful for polishing or planarizing chip interconnect/wiring material such as Al, W and especially Cu.

摘要翻译： 包含氧化剂，铜缓蚀剂，磨料颗粒的浆料组合物; 表面活性剂和聚电解质可用于抛光或平面化芯片互连/布线材料如Al，W，特别是Cu。

公开(公告)号：US5558563A

公开(公告)日：1996-09-24

申请号：US392591

申请日：1995-02-23

申请人： William J. Cote ,  Michael F. Lofaro

发明人： William J. Cote ,  Michael F. Lofaro

IPC分类号： B24B37/04 ,  B24D13/14 ,  H01L21/304 ,  B24B1/00

CPC分类号： B24B37/26 ,  B24B37/042

摘要： A method and apparatus for improved control of polishing in chemical-mechanical polishing operations is provided. The polishing is controlled by applying different amounts of pressure to the surface of a substrate during polishing. A polishing pad which includes raised portions is used to apply the varying amounts of pressure. In addition, the position, size and height of the raised portions is used to affect the amount of pressure applied.

摘要翻译： 提供了一种用于改善化学机械抛光操作中抛光控制的方法和装置。 抛光是通过在抛光期间将不同量的压力施加到基底表面来控制的。 使用包括凸起部分的抛光垫来施加变化的压力。 此外，凸起部分的位置，尺寸和高度用于影响施加的压力量。

公开(公告)号：US08481423B2

公开(公告)日：2013-07-09

申请号：US11857760

申请日：2007-09-19

申请人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

发明人： John C. Arnold ,  Griselda Bonilla ,  William J. Cote ,  Geraud Dubois ,  Daniel C. Edelstein ,  Alfred Grill ,  Elbert Huang ,  Robert D. Miller ,  Satya V. Nitta ,  Sampath Purushothaman ,  E. Todd Ryan ,  Muthumanickam Sankarapandian ,  Terry A. Spooner ,  Willi Volksen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.

公开(公告)号：US20090146211A1

公开(公告)日：2009-06-11

申请号：US12348438

申请日：2009-01-05

申请人： William J. Cote ,  Oliver D. Patterson

发明人： William J. Cote ,  Oliver D. Patterson

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/00

CPC分类号： H01L21/76264 ,  H01L21/84 ,  H01L27/1203

摘要： Structures and a method are disclosed for grounding gate-stack and/or silicon active region front-end-of-line structures on a silicon-on-insulator (SOI) substrate, which may be used as test structures for VC inspection. In one embodiment, a structure includes a grounded bulk silicon substrate having the SOI substrate thereover, the SOI substrate including a silicon-on-insulator (SOI) layer and a buried oxide (BOX) layer; the silicon active region having at least one finger element within the SOI layer, the at least one finger element isolated by a shallow trench isolation (STI) layer; and a polysilicon ground intersecting the at least one finger element and extending through the STI layer and the BOX layer to the grounded bulk silicon substrate, the polysilicon ground contacting the silicon active region and the grounded bulk silicon substrate.

摘要翻译： 公开了用于在绝缘体上硅（SOI）衬底上接地栅叠层和/或硅有源区前线结构的结构和方法，其可用作VC检验的测试结构。 在一个实施例中，结构包括其上具有SOI衬底的接地体硅衬底，SOI衬底包括绝缘体上硅（SOI）层和掩埋氧化物（BOX）层; 所述硅有源区在所述SOI层内具有至少一个指状元件，所述至少一个指状元件由浅沟槽隔离（STI）层隔离; 以及与所述至少一个指状元件相交并且穿过所述STI层和所述BOX层延伸到所述接地体硅衬底的多晶硅地，所述多晶硅接地与所述硅有源区和所述接地体硅衬底接触。

公开(公告)号：US06649531B2

公开(公告)日：2003-11-18

申请号：US09994340

申请日：2001-11-26

申请人： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

发明人： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

IPC分类号： H01L21302

CPC分类号： H01L21/76808 ,  H01L21/31633

摘要： A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

摘要翻译： 用于形成镶嵌结构的方法包括将包括第一介电层和第二介电层的双层沉积到基板上，其中第一层具有高于第二层的介电常数，并且其中第二层选自低k 包含Si，C，O和H的介电材料。使用高选择性各向异性反应离子蚀刻，将多步镶嵌结构图案化成电介质双层。 使用等离子体灰化处理从基板去除光致抗蚀剂，聚合物和后蚀刻残留物，而不损坏下面的介电层。

公开(公告)号：US06375693B1

公开(公告)日：2002-04-23

申请号：US09307123

申请日：1999-05-07

申请人： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

发明人： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

IPC分类号： C09K314

CPC分类号： H01L21/76843 ,  C09G1/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

摘要： A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as DUPONOL SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

摘要翻译： 通过化学机械平面化（CMP）在氧化剂如过氧化氢，去离子水，腐蚀抑制剂如BTA的酸性浆料和诸如DUPONOL SP的表面活性剂中选择性除去用于铜冶金的钽基衬垫，得到 在较高的衬里去除速率下，无明显去除暴露的铜和最小的凹陷。

公开(公告)号：US09213060B2

公开(公告)日：2015-12-15

申请号：US13593961

申请日：2012-08-24

申请人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

发明人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

IPC分类号： G01R31/20 ,  G01R31/28

CPC分类号： G01R31/2884

摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

公开(公告)号：US09097760B2

公开(公告)日：2015-08-04

申请号：US13593983

申请日：2012-08-24

申请人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

发明人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

IPC分类号： G01R31/20 ,  G01R31/28

CPC分类号： G01R31/2884

摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

摘要翻译： 使用其检测缺陷的测试结构和方法。 包括第一，第二和第三探针焊盘的可探测电压对比度（VC）梳状测试结构，包括接地尖齿的梳状结构，接地尖端之间的浮动尖齿，与每个浮动齿的端部耦合的开关装置， 以及将所述浮动尖齿连接到所述第二探针焊盘，并且所述第三探针焊盘是控制所述切换装置的控制焊盘。 一种可探测的VC蛇形测试结构，包括第一，第二，第三和第四探针焊盘，包括接地尖齿的梳状结构，接地尖齿之间的浮动尖齿和连接在第二和第三探针焊盘之间的每个浮动齿，切换 连接到每个浮动齿的端部并且将浮动尖齿连接到第二和第三探针焊盘的装置，第四探针焊盘是控制开关装置的控制焊盘。

公开(公告)号：US08350583B2

公开(公告)日：2013-01-08

申请号：US12539732

申请日：2009-08-12

申请人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

发明人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

IPC分类号： G01R31/20 ,  G01R1/067

CPC分类号： G01R31/2884

摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.

公开(公告)号：US20120319714A1

公开(公告)日：2012-12-20

申请号：US13593983

申请日：2012-08-24

申请人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

发明人： William J. Cote ,  Yi Feng ,  Oliver D. Patterson

IPC分类号： G01R31/02 ,  G01R1/067

CPC分类号： G01R31/2884

摘要： Test structures and method for detecting defects using the same. A probe-able voltage contrast (VC) comb test structure that includes first, second and third probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines, switching devices coupled with an end portion of each floating tine, and connecting the floating tines to the second probe pad, and the third probe pad being a control pad which controls the switching devices. A probe-able VC serpentine test structure that includes first, second, third and fourth probe pads, a comb-like structure including grounded tines, floating tines between the grounded tines and each floating tine connected together between the second and third probe pads, switching devices connected to an end portion of each floating tine and connecting the floating tines to the second and third probe pads, and the fourth probe pad being a control pad which controls the switching devices.