公开(公告)号：US20150006937A1

公开(公告)日：2015-01-01

申请号：US13931128

申请日：2013-06-28

申请人： EFRAIM ROTEM ,  ALON NAVEH ,  DORON RAJWAN ,  NADAV SHULMAN ,  ELIEZER WEISSMANN

发明人： EFRAIM ROTEM ,  ALON NAVEH ,  DORON RAJWAN ,  NADAV SHULMAN ,  ELIEZER WEISSMANN

IPC分类号： G06F1/20 ,  G06F1/32

CPC分类号： G06F1/206 ,  G06F1/203 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D50/20

摘要： In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.

摘要翻译： 在一个实施例中，一种装置包括温度传感器，用于对平台中的部件执行多个结温测量，控制器包括至少其一部分处于硬件中的逻辑。 逻辑可以从温度传感器接收多个结温度测量值，并且当结温度测量超过第一阈值时可以指示组件执行部件的第一次掉电动作，并且可以指示组件执行第二次掉电 当基于结温度测量的多重性的平均结温超过第二阈值时，组分的作用。 公开和要求保护其他实施例。

公开(公告)号：US20180232330A1

公开(公告)日：2018-08-16

申请号：US15430345

申请日：2017-02-10

申请人： ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  DORON RAJWAN ,  HISHAM ABU SALAH ,  ARIEL GUR ,  Guy M. THERIEN ,  RUSSELL J. FENGER

发明人： ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  DORON RAJWAN ,  HISHAM ABU SALAH ,  ARIEL GUR ,  Guy M. THERIEN ,  RUSSELL J. FENGER

IPC分类号： G06F13/24 ,  G06F1/32 ,  G06F9/30

CPC分类号： G06F13/24 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/44 ,  G06F9/4411

摘要： Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

公开(公告)号：US20180095932A1

公开(公告)日：2018-04-05

申请号：US15281651

申请日：2016-09-30

申请人： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

发明人： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

IPC分类号： G06F15/82 ,  G06F1/32

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3293 ,  G06F17/5054 ,  G06F2217/78 ,  G06F2217/80

摘要： In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US20160004296A1

公开(公告)日：2016-01-07

申请号：US14322185

申请日：2014-07-02

申请人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

发明人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/171

摘要： Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了与自主C状态机制和计算引擎对准相关的方法和设备，以提高处理器功率效率。 一个实施例基于用于进入和退出包装C状态的能量消耗值，半导体封装在包装C中保持在预先状态的时间量以及一个或多个盈亏平衡时间来确定半导体封装是否应该进入封装C状态 各种封装C状态之间的点。 另一个实施例检测处理器的成像计算单元相对于处理器的一个或多个其它计算单元进入低功耗状态的延迟。 该逻辑使成像计算单元响应于延迟的检测而进入低功耗状态。 还公开并要求保护其他实施例。

公开(公告)号：US20150370304A1

公开(公告)日：2015-12-24

申请号：US14313597

申请日：2014-06-24

申请人： HISHAM ABU SALAH ,  ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  JAY D. SCHWARTZ ,  SHARAD C. TRIPATHI

发明人： HISHAM ABU SALAH ,  ELIEZER WEISSMANN ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  JAY D. SCHWARTZ ,  SHARAD C. TRIPATHI

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3206 ,  G06F1/3293 ,  Y02D10/126

摘要： Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

摘要翻译： 上述技术可以提高处理器，SoC或计算系统的功率性能效率。 这里描述的实施例响应于在低处理器利用周期内检测到高活动突发的发生，允许将时钟信号的频率增加到峰值频率值。 功率管理单元可以在低或空闲处理器利用周期期间累积预算，并且可以确定高活动信号的突发的活动级别。 如果高活动突发级别超过第一阈值并且累积预算值超过第二阈值，则PMU可以增加提供给处理核心的时钟信号的频率。

公开(公告)号：US20160335090A1

公开(公告)日：2016-11-17

申请号：US15221557

申请日：2016-07-27

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F9/38 ,  G06F12/1027 ,  G06F12/0875

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US20170153984A1

公开(公告)日：2017-06-01

申请号：US15394458

申请日：2016-12-29

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F12/1027 ,  G06F12/1009

CPC分类号： G06F9/3851 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US20170109281A1

公开(公告)日：2017-04-20

申请号：US15394539

申请日：2016-12-29

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F12/0811 ,  G06F12/1009 ,  G06F12/1027

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US20170109294A1

公开(公告)日：2017-04-20

申请号：US15394493

申请日：2016-12-29

申请人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

发明人： ELIEZER WEISSMANN ,  KARTHIKEYAN KARTHIK VAITHIANATHAN ,  YOAV ZACH ,  BORIS GINZBURG ,  RONNY RONEN

IPC分类号： G06F12/1045 ,  G06F12/084 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/1072 ,  G06F12/0811 ,  G06F12/0875

CPC分类号： G06F9/3851 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：US20150277538A1

公开(公告)日：2015-10-01

申请号：US14225960

申请日：2014-03-26

申请人： AHMAD YASIN ,  NIR ROSENZWEIG ,  ELIEZER WEISSMANN ,  EFRAIM EFI ROTEM

发明人： AHMAD YASIN ,  NIR ROSENZWEIG ,  ELIEZER WEISSMANN ,  EFRAIM EFI ROTEM

IPC分类号： G06F1/32

CPC分类号： G06F1/3243 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/152

摘要： A processing device implementing performance scalability prediction is disclosed. A processing device of the disclosure includes a first counter to increment with each cycle of the processing device in which threads of the processing device are active. The processing device further includes a second counter to increment with each cycle of the processing device in which execution units of the processing device are stalled for one of the threads, and an access request from the one of the threads to memory external to the processing device is pending.

摘要翻译： 公开了一种实现性能可伸缩性预测的处理装置。 本公开的处理装置包括：第一计数器，其随处理装置的每个周期递增，其中处理装置的线程处于活动状态。 所述处理装置还包括第二计数器，其随着所述处理装置的每个周期递增，其中所述处理装置的执行单元被停止用于所述线程之一，以及从所述线程中的一个到所述处理装置外部的存储器的访问请求 等待中。