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    Process for producing a nanoelement arrangement, and nanoelement arrangement
    3.
    发明授权
    Process for producing a nanoelement arrangement, and nanoelement arrangement 有权
    用于制备纳米元件排列的方法和纳米元件排列

    公开(公告)号：US07183131B2

    公开(公告)日：2007-02-27

    申请号：US10712767

    申请日：2003-11-12

    申请人： Eugen Unger ,  Georg Stefan Dusberg ,  Andrew Graham ,  Maik Liebau

    发明人： Eugen Unger ,  Georg Stefan Dusberg ,  Andrew Graham ,  Maik Liebau

    IPC分类号： H01L51/40

    CPC分类号： H01L51/0048 ,  B82Y10/00 ,  Y10S438/903 ,  Y10S977/891

    摘要： A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material.Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.

    摘要翻译： 用于制备纳米元件排列和纳米元件排列的方法。 至少部分地用催化剂材料覆盖第一纳米元素以催化纳米元素的生长。 此外，在催化剂材料上生长至少一个第二纳米元素。 而且，具有第一纳米元素的纳米元件排列，其上至少一个预定区域被催化剂材料覆盖以催化纳米元素的生长，以及在催化剂材料上生长的至少一个第二纳米元素。

    Memory device for storing electric charge, and method for fabricating it
    4.
    发明申请
    Memory device for storing electric charge, and method for fabricating it 审中-公开
    用于存储电荷的存储装置及其制造方法

    公开(公告)号：US20060186451A1

    公开(公告)日：2006-08-24

    申请号：US11363991

    申请日：2006-02-28

    申请人： Georg Dusberg ,  Andrew Graham ,  Franz Kreupl

    发明人： Georg Dusberg ,  Andrew Graham ,  Franz Kreupl

    IPC分类号： H01L29/94 ,  H01L21/8242

    CPC分类号： G11C13/0033 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/16 ,  H01L27/10817 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/91 ,  H01L51/0048 ,  H01L51/0052

    摘要： The present device relates to memory devices for storing electric charge having memory cells and transistors arranged spatially next to them, and relates in particular to memory devices having memory cells with a high capacitance. In the memory cells which form a memory device to which the invention relates, there is a substrate and at least one memory cell which is arranged on the substrate and includes a first electrode element, which is electrically connected to the substrate, an insulation layer, which has been applied to the first electrode element, and a second electrode element, which has been applied to the insulation layer and is electrically insulated from the first electrode element.

    摘要翻译： 本装置涉及用于存储电荷的存储装置，该电荷具有存储单元和在空间上排列的晶体管，特别涉及具有高电容的存储单元的存储器件。 在形成本发明所涉及的存储器件的存储器单元中，存在一个衬底和至少一个存储单元，其被布置在衬底上，并且包括与衬底电连接的第一电极元件，绝缘层， 已经施加到第一电极元件的第二电极元件和已经施加到绝缘层并且与第一电极元件电绝缘的第二电极元件。

    Nanotube array and method for producing a nanotube array
    6.
    发明授权
    Nanotube array and method for producing a nanotube array 失效
    纳米管阵列及其制造方法

    公开(公告)号：US07635867B2

    公开(公告)日：2009-12-22

    申请号：US10476663

    申请日：2002-05-16

    申请人： Andrew Graham ,  Franz Hofmann ,  Johannes Kretz ,  Franz Kreupl ,  Richard Luyken ,  Wolfgang Rösner

    发明人： Andrew Graham ,  Franz Hofmann ,  Johannes Kretz ,  Franz Kreupl ,  Richard Luyken ,  Wolfgang Rösner

    IPC分类号： H01L31/0312

    CPC分类号： H01L51/0048 ,  B82Y10/00 ,  C01B32/05 ,  G01N27/127 ,  G11C13/025 ,  H01L51/0595

    摘要： A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.

    摘要翻译： 纳米管阵列及其制造方法。 纳米管阵列具有衬底，催化剂层，其包括在衬底的表面上的一个或多个子区域，和布置在催化剂层表面上的平行于衬底表面的至少一个纳米管。 所述至少一个纳米管平行于衬底的表面布置，导致至少一个纳米管的平面布置。 因此，本发明的纳米管阵列适用于与传统的硅微电子耦合。 因此，根据本发明，可以将纳米管阵列电连接到宏观半导体电子器件。 此外，根据本发明的纳米管阵列可以在衬底和催化剂层之间具有电绝缘层。 该电绝缘层优选地具有使得至少一个纳米管在其端部部分处于电绝缘层上并且在其中心部分未被覆盖的形貌。 由于至少一个纳米管的表面部分未被覆盖，纳米管的未被覆盖的表面可以用作主动传感器表面。 例如，纳米管的未覆盖表面可以与围绕纳米管阵列的气氛进行操作接触。 在某些气体的存在下，纳米管的电阻显着变化。 因此，由于纳米管是透明和未覆盖的，所以纳米管阵列可用于许多传感器应用中。

    Integrated electronic component
    7.
    发明授权
    Integrated electronic component 有权
    集成电子元件

    公开(公告)号：US07326465B2

    公开(公告)日：2008-02-05

    申请号：US11211168

    申请日：2005-08-23

    申请人： Robert Seidel ,  Franz Kreupl ,  Andrew Graham

    发明人： Robert Seidel ,  Franz Kreupl ,  Andrew Graham

    IPC分类号： B32B9/00

    CPC分类号： H01L21/76876 ,  B82Y10/00 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53276 ,  H01L2221/1078 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10T428/12535 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/24917 ,  Y10T428/30 ,  H01L2924/00

    摘要： An integrated electronic component having a substrate, a metal multilayer system, which is arranged at least on regions of the substrate, and a nonconductive layer, which is arranged on the metal multilayer system and has at least one contact hole, in which at least one carbon nanotube is grown on the metal multilayer system at the bottom of the contact hole. The metal multilayer system includes a high-melting metal layer, a metal separating layer, a catalyst layer, and a final metal separating layer. The high-melting metal layer is composed of at least one of tantalum, molybdenum, and tungsten. The metal separating layer is composed of aluminum, gold, or silver. The catalyst layer is composed of at least one of iron, cobalt, nickel, yttrium, titanium, platinum, and palladium, and a combination thereof. The final metal separating layer, which is arranged above the catalyst layer, is composed of aluminum.

    摘要翻译： 一种集成电子部件，其具有衬底，至少布置在所述衬底的区域上的金属多层系统和非导电层，所述非导电层布置在所述金属多层系统上并具有至少一个接触孔，其中至少一个 碳纳米管在接触孔底部的金属多层体系上生长。 金属多层体系包括高熔点金属层，金属分离层，催化剂层和最终金属分离层。 高熔点金属层由钽，钼和钨中的至少一种构成。 金属分离层由铝，金或银构成。 催化剂层由铁，钴，镍，钇，钛，铂和钯中的至少一种及其组合构成。 设置在催化剂层上方的最终金属分离层由铝构成。

    Integrated electronic component
    10.
    发明申请
    Integrated electronic component 有权
    集成电子元件

    公开(公告)号：US20060234080A1

    公开(公告)日：2006-10-19

    申请号：US11211168

    申请日：2005-08-23

    申请人： Robert Seidel ,  Franz Kreupl ,  Andrew Graham

    发明人： Robert Seidel ,  Franz Kreupl ,  Andrew Graham

    IPC分类号： C03C27/00 ,  B32B15/04 ,  B32B9/00

    CPC分类号： H01L21/76876 ,  B82Y10/00 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53276 ,  H01L2221/1078 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10T428/12535 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/24917 ,  Y10T428/30 ,  H01L2924/00

    摘要： An integrated electronic component having a substrate, a metal multilayer system, which is arranged at least on regions of the substrate, and a nonconductive layer, which is arranged on the metal multilayer system and has at least one contact hole, in which at least one carbon nanotube is grown on the metal multilayer system at the bottom of the contact hole. The metal multilayer system includes a high-melting metal layer, a metal separating layer, a catalyst layer, and a final metal separating layer. The high-melting metal layer is composed of at least one of tantalum, molybdenum, and tungsten. The metal separating layer is composed of aluminum, gold, or silver. The catalyst layer is composed of at least one of iron, cobalt, nickel, yttrium, titanium, platinum, and palladium, and a combination thereof. The final metal separating layer, which is arranged above the catalyst layer, is composed of aluminum.

    摘要翻译： 一种集成电子部件，其具有基板，至少布置在所述基板的区域上的金属多层系统和非导电层，所述非导电层布置在所述金属多层系统上并且具有至少一个接触孔，其中至少一个 碳纳米管在接触孔底部的金属多层体系上生长。 金属多层体系包括高熔点金属层，金属分离层，催化剂层和最终金属分离层。 高熔点金属层由钽，钼和钨中的至少一种构成。 金属分离层由铝，金或银构成。 催化剂层由铁，钴，镍，钇，钛，铂和钯中的至少一种及其组合构成。 设置在催化剂层上方的最终金属分离层由铝构成。