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    Non-volatile memory cells and method for fabricating non-volatile memory cells
    1.
    发明申请
    Non-volatile memory cells and method for fabricating non-volatile memory cells 审中-公开
    非易失性存储单元和用于制造非易失性存储单元的方法

    公开(公告)号：US20070096198A1

    公开(公告)日：2007-05-03

    申请号：US11262309

    申请日：2005-10-28

    申请人： Franz Hofmann ,  Johannes Luyken ,  Michael Specht ,  Wolfgang Rosner

    发明人： Franz Hofmann ,  Johannes Luyken ,  Michael Specht ,  Wolfgang Rosner

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7923 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/785

    摘要： The invention relates to non-volatile memory cells. Further, the invention relates to a method for fabricating non-volatile memory cells. Memory cells are formed on a semiconductor wafer having a protruding element with a top surface. A transistor is formed having a first part, a second part, and a third part. The first part includes a first junction region and a first charge trapping layer on the top surface. The second part includes a second junction region and charge trapping layer on the top surface. The third part has a gate electrode and a gate dielectric layer at least partially on sidewalls of the protruding element. The gate electrode contacts the first and second charge trapping layers.

    摘要翻译： 本发明涉及非易失性存储单元。 此外，本发明涉及一种制造非易失性存储单元的方法。 存储单元形成在具有顶表面的突出元件的半导体晶片上。 晶体管形成有第一部分，第二部分和第三部分。 第一部分包括顶表面上的第一接合区域和第一电荷俘获层。 第二部分包括顶表面上的第二结区和电荷捕获层。 第三部分至少部分地在突出元件的侧壁上具有栅极电极和栅极电介质层。 栅电极接触第一和第二电荷捕获层。

    Semiconductor memory device
    3.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060267084A1

    公开(公告)日：2006-11-30

    申请号：US11139976

    申请日：2005-05-31

    申请人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele ,  Johannes Luyken

    发明人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele ,  Johannes Luyken

    IPC分类号： H01L29/76

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7393

    摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极 具有栅极电介质层和栅电极的结构。 所述栅极结构布置在所述漏极区域和所述源极区域之间。 提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

    Method for producing a substrate
    5.
    发明授权
    Method for producing a substrate 有权
    制造基板的方法

    公开(公告)号：US07611928B2

    公开(公告)日：2009-11-03

    申请号：US10968846

    申请日：2004-10-18

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76254

    摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

    摘要翻译： 衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。 第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层 并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。 在半导体层上形成晶体管。

    Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration
    6.
    发明授权
    Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration 失效
    具有存储单元体区域的半导体存储器组件具有凹陷和渐变的掺杂剂浓度

    公开(公告)号：US07598543B2

    公开(公告)日：2009-10-06

    申请号：US11438883

    申请日：2006-05-23

    申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

    摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

    High-density NROM-FINFET
    9.
    发明授权
    High-density NROM-FINFET 失效
    高密度NROM-FINFET

    公开(公告)号：US07208794B2

    公开(公告)日：2007-04-24

    申请号：US11073017

    申请日：2005-03-04

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Wolfgang Roesner ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/905

    摘要： Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence in the longitudinal direction of the rib. The rib has an essentially rectangular shape with an upper side of the rib and rib side faces lying opposite. A memory layer is configured for programming the memory cell, arranged on the upper side of the rib spaced apart by a first insulator layer, and projects in the normal direction of the one rib side face over one of the rib side faces so that the one rib side face and the upper side of the rib form an edge for injecting charge carriers from the channel region into the memory layer. A gate electrode is spaced apart from the one rib side face by a second insulator layer and from the memory layer by a third insulator layer, electrically insulated from the channel region, and configured to control its electrical conductivity.

    摘要翻译： 具有存储单元的半导体存储器，每个存储单元包括第一和第二导电掺杂的接触区域和布置在其间的沟道区域，所述沟道区域形成在由半导体材料制成的网状肋状物中， 肋骨 肋具有基本上矩形的形状，肋的上侧和肋侧面相对。 存储层被配置为对存储单元进行编程，布置在由第一绝缘体层间隔开的肋的上侧，并且沿着一个肋侧面的一个肋侧面的法线方向突出，使得一个 肋侧面和肋的上侧形成用于将电荷载流子从沟道区域注入到存储层中的边缘。 栅电极通过第二绝缘体层与一个肋侧面间隔开，并且通过与沟道区电绝缘并且被配置为控制其导电性的第三绝缘体层与存储层隔开。

    Non-volatile memory cells and methods for fabricating non-volatile memory cells
    10.
    发明申请
    Non-volatile memory cells and methods for fabricating non-volatile memory cells 有权
    非易失性存储单元和用于制造非易失性存储单元的方法

    公开(公告)号：US20070018201A1

    公开(公告)日：2007-01-25

    申请号：US11187693

    申请日：2005-07-22

    申请人： Michael Specht ,  Franz Hofmann ,  Johannes Luyken

    发明人： Michael Specht ,  Franz Hofmann ,  Johannes Luyken

    IPC分类号： H01L27/10

    CPC分类号： H01L27/11568 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/785

    摘要： The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.

    摘要翻译： 本发明涉及一种用于制造堆叠的非易失性存储单元的方法。 此外，本发明涉及堆叠的非易失性存储单元。 本发明特别涉及具有非易失性堆叠存储单元的非易失性NAND存储器的领域。 层叠的非易失性存储单元形成在具有体半导体基板和SOI半导电层的半导体晶片上，并且被布置为体FinFET晶体管，并且SOI FinFet晶体管布置在体FinFET晶体管的顶部 。 FinFET晶体管和SOI FinFet晶体管都连接到公共的电荷俘获层。 具有侧壁的字线被布置在所述图案化的电荷捕获层的顶部上，并且间隔氧化物层被布置在所述字线的侧壁上。