摘要:
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.
摘要:
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.
摘要:
An explanation is given of, inter alia, a circuit arrangement in which an intermediate layer (160) made of a dielectric material is arranged between two metal layers (102 and 104). The intermediate layer (160) is designed in such a way that the capacitance per unit area between the connection layers (102, 104) is greater than 0.5 fF/μm2.
摘要:
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.
摘要:
Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.
摘要:
A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.
摘要:
An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.
摘要:
A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.
摘要:
Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited.
摘要:
An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.