公开(公告)号：US06962879B2

公开(公告)日：2005-11-08

申请号：US09820694

申请日：2001-03-30

申请人： Helen H. Zhu ,  David R. Pirkle ,  S. M. Reza Sadjadi ,  Andrew S. Li

发明人： Helen H. Zhu ,  David R. Pirkle ,  S. M. Reza Sadjadi ,  Andrew S. Li

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76813

摘要： A semiconductor manufacturing process wherein silicon nitride is plasma etched with selectivity to an overlying and/or underlying dielectric layer such as a silicon oxide or low-k material. The etchant gas includes a fluorocarbon reactant and an oxygen reactant, the ratio of the flow rate of the oxygen reactant to that of the fluorocarbon reactant being no greater than 1.5. The etch rate of the silicon nitride can be at least 5 times higher than that of the oxide. Using a combination of CH3F and O2 with optional carrier gasses such as Ar and/or N2, it is possible to obtain nitride:oxide etch rate selectivities of over 40:1. The process is useful for simultaneously removing silicon nitride in 0.25 micron and smaller contact or via openings and wide trenches in forming structures such as damascene and self-aligned structures.

摘要翻译： 半导体制造工艺，其中氮化硅被等离子体蚀刻，对上覆和/或下层介电层（例如氧化硅或低k材料）具有选择性。 蚀刻剂气体包括氟碳反应物和氧反应物，氧反应物的流速与氟碳反应物的流速之比不大于1.5。 氮化硅的蚀刻速率可以比氧化物的蚀刻速度高5倍以上。 使用CH 3 3 F和O 2 2的组合与可选的载气如Ar和/或N 2 N组合，可以获得氮化物 ：氧化物蚀刻速率选择性超过40：1。 该方法对于同时去除0.25微米和更小的接触或通孔开口和宽沟槽中的氮化硅在形成结构如镶嵌和自对准结构中是有用的。

公开(公告)号：US06670278B2

公开(公告)日：2003-12-30

申请号：US09820726

申请日：2001-03-30

申请人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  James Bowers ,  Michael Goss

发明人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  James Bowers ,  Michael Goss

IPC分类号： H01L21302

CPC分类号： H01L21/7681 ,  H01L21/31116 ,  H01L21/76807

摘要： The invention provides a process for plasma etching silicon carbide with selectivity to an overlapping and/or underlying dielectric layer of material. The etching gas includes a hydrogen-containing fluorocarbon gas such as CH3F, an oxygen-containing gas such as O2 and an optional carrier gas such as Ar. The dielectric material can comprise silicon dioxide, silicon nitride, silicon oxynitride or various low-k dielectric materials including organic low-k materials. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrates.

公开(公告)号：US06794293B2

公开(公告)日：2004-09-21

申请号：US09972765

申请日：2001-10-05

申请人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

发明人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/02126 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76804 ,  H01L21/76808

摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

摘要翻译： 本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。 在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。 在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。 优选地，该方法用于不具有中间蚀刻停止层的低k电介质。 另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。 作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

公开(公告)号：US06909195B2

公开(公告)日：2005-06-21

申请号：US10826211

申请日：2004-04-16

申请人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

发明人： SiYi Li ,  S. M. Reza Sadjadi ,  David R. Pirkle ,  Steve Lassig ,  Sean Kang ,  Vinay Pohray ,  Peter Cirigliano

IPC分类号： H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/31116 ,  H01L21/02126 ,  H01L21/31138 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76804 ,  H01L21/76808

摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

公开(公告)号：US07311852B2

公开(公告)日：2007-12-25

申请号：US09820695

申请日：2001-03-30

申请人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  James V. Tietz ,  Bryan A. Helmer

发明人： Si Yi Li ,  Helen H. Zhu ,  S. M. Reza Sadjadi ,  James V. Tietz ,  Bryan A. Helmer

IPC分类号： H01L21/3065

CPC分类号： H01L21/7681 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807

摘要： A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

摘要翻译： 一种半导体制造工艺，其中低k电介质层被等离子体蚀刻，对上覆掩模层具有选择性。 蚀刻剂气体可以是无氧的并且包括氟碳反应物，氮反应物和任选的载气，所述碳氟反应物和氮反应物以流速供给到等离子体蚀刻反应器的室，使得碳氟化合物反应物流速为 小于氮气反应物流量。 低k电介质层的蚀刻速率可以比二氧化硅，氮化硅，氮氧化硅或碳化硅掩模层的蚀刻速率高至少5倍。 该方法对于在形成结构如镶嵌结构中蚀刻0.25微米和较小的接触或通孔开口是有用的。

公开(公告)号：US20090311871A1

公开(公告)日：2009-12-17

申请号：US12139124

申请日：2008-06-13

申请人： Helen H. Zhu ,  Peter Cirigliano ,  S. M. Reza Sadjadi

发明人： Helen H. Zhu ,  Peter Cirigliano ,  S. M. Reza Sadjadi

IPC分类号： H01L21/302

CPC分类号： H01L21/31138 ,  H01L21/31144

摘要： A method for forming etch features in an etch layer over a substrate and below an organic ARC layer, which is below an immersion lithography photoresist mask is provided. The substrate with the etch layer, organic ARC layer, and immersion lithography photoresist mask is placed into a processing chamber. The organic ARC layer is opened. The organic ARC layer opening comprises flowing an organic ARC open gas mixture into the processing chamber, wherein the organic ARC open gas mixture comprises an etchant gas and a polymerization gas comprising CO, forming an organic ARC open plasma from the organic ARC open gas mixture, etching the organic ARC layer with the organic ARC open plasma until the organic ARC layer is opened, and stopping the flow of organic ARC open gas mixture into the processing chamber before the etch layer is completely etched.

摘要翻译： 提供了一种用于在衬底上方的蚀刻层中形成蚀刻特征的方法，并且在浸没式光刻光刻胶掩模下面的有机ARC层下面形成蚀刻特征。 将具有蚀刻层，有机ARC层和浸没光刻光刻胶掩模的基板放置在处理室中。 有机ARC层打开。 有机ARC层开口包括将有机ARC开放气体混合物流入处理室，其中有机ARC开放气体混合物包含蚀刻剂气体和包含CO的聚合气体，从有机ARC开放气体混合物形成有机ARC开放等离子体， 用有机ARC打开的等离子体蚀刻有机ARC层直到有机ARC层被打开，并且在刻蚀层被完全蚀刻之前停止有机ARC开放气体混合物流入处理室。

公开(公告)号：US07049052B2

公开(公告)日：2006-05-23

申请号：US10435130

申请日：2003-05-09

申请人： Hanzhong Xiao ,  Helen H. Zhu ,  Kuo-Lung Tang ,  S. M. Reza Sadjadi

发明人： Hanzhong Xiao ,  Helen H. Zhu ,  Kuo-Lung Tang ,  S. M. Reza Sadjadi

IPC分类号： G03F7/00 ,  G03F7/36

CPC分类号： H01L21/31138 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31144

摘要： A method for etching a feature in a layer is provided. An underlayer of a polymer material is formed over the layer. A top image layer is formed over the underlayer. The top image layer is exposed to patterned radiation. A pattern is developed in the top image layer. The pattern is transferred from the top image layer to the underlayer with a reducing dry etch. The layer is etched through the underlayer, where the top image layer is completely removed and the underlayer is used as a pattern mask during the etching the layer to transfer the pattern from the underlayer to the layer.

公开(公告)号：US08268118B2

公开(公告)日：2012-09-18

申请号：US12711420

申请日：2010-02-24

申请人： Sangheon Lee ,  Dae-Han Choi ,  Jisoo Kim ,  Peter Cirigliano ,  Zhisong Huang ,  Robert Charatan ,  S. M. Reza Sadjadi

发明人： Sangheon Lee ,  Dae-Han Choi ,  Jisoo Kim ,  Peter Cirigliano ,  Zhisong Huang ,  Robert Charatan ,  S. M. Reza Sadjadi

IPC分类号： H01L21/3065

CPC分类号： C23F4/00 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  Y10S438/947

摘要： A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

摘要翻译： 提供了一种在蚀刻层中形成特征的方法。 在蚀刻层上形成光致抗蚀剂层。 图案化光致抗蚀剂层以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征。 在光致抗蚀剂层和光致抗蚀剂特征的底部上形成控制层。 在光致抗蚀剂特征和控制层的侧壁上沉积保形层以减少光刻胶特征的临界尺寸。 控制层的开口打开，控制层突破性化学。 特征被蚀刻到蚀刻层中，其蚀刻化学性质不同于控制层突破性化学，其中控制层比蚀刻化学性质比共形层更耐蚀刻蚀刻。

公开(公告)号：US08172980B2

公开(公告)日：2012-05-08

申请号：US12202043

申请日：2008-08-29

申请人： S. M. Reza Sadjadi ,  Zhi-Song Huang

发明人： S. M. Reza Sadjadi ,  Zhi-Song Huang

IPC分类号： C23F1/00 ,  H01L21/306 ,  C23C16/00

CPC分类号： H01L21/7682 ,  H01J37/32623 ,  H01J37/32633 ,  H01J37/32642 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

摘要翻译： 提供了用于降低半导体器件布线之间的电容的方法。 在电介质层上形成牺牲层。 多个特征被蚀刻到牺牲层和电介质层中。 功能填充填充材料。 去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。 填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。 通过收缩侧壁沉积将间隙蚀刻到介电层中。 去除填充材料和收缩侧壁沉积。

公开(公告)号：US07977242B2

公开(公告)日：2011-07-12

申请号：US12366113

申请日：2009-02-05

申请人： S. M. Reza Sadjadi ,  Lumin Li ,  Andrew R. Romano

发明人： S. M. Reza Sadjadi ,  Lumin Li ,  Andrew R. Romano

IPC分类号： H01L21/461 ,  H01L21/311

CPC分类号： H01L21/0337

摘要： A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.

摘要翻译： 通过在无机掩模层上形成有机掩模层，在有机掩模层上形成含硅掩模层，在含硅掩模层上形成图案化掩模层，蚀刻，提供蚀刻层中提供特征的方法 通过图案化掩模的含硅掩模层，在蚀刻的含硅掩模层上沉积聚合物，在聚合物上沉积含硅膜，平坦化含硅膜，选择性地除去离开含硅膜的聚合物 蚀刻有机层，并蚀刻无机层。