公开(公告)号：US20110223749A1

公开(公告)日：2011-09-15

申请号：US12913062

申请日：2010-10-27

申请人： Hiromu SHIOMI ,  Yu Saitoh ,  Kazuhide Sumiyoshi ,  Akihiro Hachigo ,  Makoto Kiyama ,  Seiji Nakahata

发明人： Hiromu SHIOMI ,  Yu Saitoh ,  Kazuhide Sumiyoshi ,  Akihiro Hachigo ,  Makoto Kiyama ,  Seiji Nakahata

IPC分类号： H01L21/205 ,  H01L21/3063

CPC分类号： H01L21/0262 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/7813

摘要： The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm−2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.

摘要翻译： 本发明的形成氮化物半导体外延层的方法包括以下步骤：在具有低于或等于1×107cm-2的位错密度的氮化物半导体衬底上生长至少一层氮化物半导体外延层，其中化学分解层插入 其间，化学分解层至少用气体或电解液进行化学分解，并且至少在气体或电解液中的化学分解层至少在生长氮化物半导体外延的步骤期间或之后分解 从而将氮化物半导体外延层与氮化物半导体衬底分离。 由此形成与氮化物半导体基板分离时受损少的高质量氮化物半导体外延层。

公开(公告)号：US08349078B2

公开(公告)日：2013-01-08

申请号：US12913062

申请日：2010-10-27

申请人： Hiromu Shiomi ,  Yu Saitoh ,  Kazuhide Sumiyoshi ,  Akihiro Hachigo ,  Makoto Kiyama ,  Seiji Nakahata

发明人： Hiromu Shiomi ,  Yu Saitoh ,  Kazuhide Sumiyoshi ,  Akihiro Hachigo ,  Makoto Kiyama ,  Seiji Nakahata

IPC分类号： C30B25/20 ,  C30B25/22 ,  C30B29/40 ,  H01L21/306

CPC分类号： H01L21/0262 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/7813

摘要： The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm−2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.

摘要翻译： 本发明的形成氮化物半导体外延层的方法包括以下步骤：在具有低于或等于1×107cm-2的位错密度的氮化物半导体衬底上生长至少一层氮化物半导体外延层，其中化学分解层插入 其间，化学分解层至少用气体或电解液进行化学分解，并且至少在气体或电解液中的化学分解层至少在生长氮化物半导体外延的步骤期间或之后分解 从而将氮化物半导体外延层与氮化物半导体衬底分离。 由此形成与氮化物半导体基板分离时受损少的高质量氮化物半导体外延层。

公开(公告)号：US08502310B2

公开(公告)日：2013-08-06

申请号：US13124934

申请日：2009-10-20

申请人： Hiromu Shiomi ,  Kazuhide Sumiyoshi ,  Yu Saitoh ,  Makoto Kiyama

发明人： Hiromu Shiomi ,  Kazuhide Sumiyoshi ,  Yu Saitoh ,  Makoto Kiyama

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/475 ,  H01L29/66712 ,  H01L29/861 ,  H01L29/872

摘要： Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm−3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle θ of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle θ. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.

摘要翻译： 提供具有能够减少漏电流的结构的III族氮化物半导体电子器件。 层压体11包括基板13和III族氮化物半导体外延膜15.基板13由载流子浓度大于1×1018cm-3的III族氮化物半导体构成。 外延结构15包括III族氮化物半导体外延膜17.基板13的第一面13a相对于沿c轴方向延伸的轴线Cx以大于5度的角度θ倾斜。 法向量VN和c轴矢量VC形成角度θ。 III族氮化物半导体外延膜17包括沿着与第一面13a的法线方向依次排列的第一，第二和第三区域17a，17b和17c。 第三区域17c的位错密度小于第一区域17a的位错密度。 第二区域17b的位错密度小于基板13的位错密度。

公开(公告)号：US20110198693A1

公开(公告)日：2011-08-18

申请号：US13124934

申请日：2009-10-20

申请人： Hiromu Shiomi ,  Kazuhide Sumiyoshu ,  Yu Saitoh ,  Makoto Kiyama

发明人： Hiromu Shiomi ,  Kazuhide Sumiyoshu ,  Yu Saitoh ,  Makoto Kiyama

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/205

CPC分类号： H01L29/7802 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/475 ,  H01L29/66712 ,  H01L29/861 ,  H01L29/872

摘要： Provided is a III nitride semiconductor electronic device having a structure capable of reducing leakage current. A laminate 11 includes a substrate 13 and a III nitride semiconductor epitaxial film 15. The substrate 13 is made of a III nitride semiconductor having a carrier concentration of more than 1×1018 cm−3. The epitaxial structure 15 includes a III nitride semiconductor epitaxial film 17. A first face 13a of the substrate 13 is inclined at an angle θ of more than 5 degrees with respect to an axis Cx extending in a direction of the c-axis. A normal vector VN and a c-axis vector VC make the angle θ. The III nitride semiconductor epitaxial film 17 includes first, second and third regions 17a, 17b and 17c arranged in order in a direction of a normal to the first face 13a. A dislocation density of the third region 17c is smaller than that of the first region 17a. A dislocation density of the second region 17b is smaller than that of the substrate 13.

摘要翻译： 提供具有能够减少漏电流的结构的III族氮化物半导体电子器件。 层压体11包括基板13和III族氮化物半导体外延膜15.基板13由载流子浓度大于1×1018cm-3的III族氮化物半导体构成。 外延结构15包括III族氮化物半导体外延膜17.衬底13的第一面13a以角度倾斜; 相对于沿c轴方向延伸的轴线Cx大于5度。 法向量VN和c轴向量VC使得角度和角度。 III族氮化物半导体外延膜17包括沿着与第一面13a的法线方向依次排列的第一，第二和第三区域17a，17b和17c。 第三区域17c的位错密度小于第一区域17a的位错密度。 第二区域17b的位错密度小于基板13的位错密度。

公开(公告)号：US07998836B1

公开(公告)日：2011-08-16

申请号：US12912932

申请日：2010-10-27

申请人： Hiromu Shiomi ,  Shinsuke Fujiwara ,  Yu Saitoh ,  Makoto Kiyama

发明人： Hiromu Shiomi ,  Shinsuke Fujiwara ,  Yu Saitoh ,  Makoto Kiyama

IPC分类号： H01L21/30

CPC分类号： H01L29/66219 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/861 ,  H01L29/872

摘要： A method of fabricating a gallium nitride-based semiconductor electronic device is provided, the method preventing a reduction in adhesiveness between a gallium nitride-based semiconductor layer and a conductive substrate. A substrate 11 is prepared. The substrate 11 has a first surface 11a and a second surface 11b, the first surface 11a allowing a gallium nitride-based semiconductor to be deposited thereon. The substrate 11 includes a support 13 of a material different from the gallium nitride-based semiconductor. The support is exposed on the second surface 11b of the substrate 11. An array of grooves 15 is provided in the second surface 11b. A semiconductor region including at least one gallium nitride-based semiconductor layer is deposited on the first surface 11a of the substrate 11, and thereby an epitaxial substrate E is fabricated. A conductive substrate 33 is bonded to the epitaxial substrate E such that the semiconductor region 17 is provided between the first surface 11a of the substrate 11 and the conductive substrate E. Subsequently, the second surface 11b is irradiated with laser light for laser lift-off.

摘要翻译： 提供了一种制造氮化镓基半导体电子器件的方法，该方法防止了氮化镓基半导体层与导电基片之间的粘附性的降低。 制备基板11。 基板11具有第一表面11a和第二表面11b，第一表面11a允许沉积氮化镓基半导体。 基板11包括与氮化镓基半导体不同的材料的支撑体13。 支撑体暴露在基板11的第二表面11b上。在第二表面11b中设置有一组槽15。 包括至少一个氮化镓基半导体层的半导体区域沉积在衬底11的第一表面11a上，由此制造外延衬底E。 将导电基板33接合到外延基板E，使得半导体区域17设置在基板11的第一表面11a和导电基板E之间。接着，用激光照射激光剥离第二表面11b 。

公开(公告)号：US08816398B2

公开(公告)日：2014-08-26

申请号：US13824043

申请日：2011-07-06

申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/15 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/778 ,  H01L29/0696 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

摘要： There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.

摘要翻译： 提供了一种垂直GaN基半导体器件，其中可以使用p型GaN势垒层改善导通电阻，同时提高击穿电压特性。 半导体器件包括再生长层27，其包括位于开口28的壁表面上的沟道，其端面被覆盖的p型势垒层6，与p型势垒层接触的源极层7， 位于再生长层上的栅电极G和位于开口周围的源电极S. 在半导体器件中，源极层具有超晶格结构，该超晶格结构由包括具有比p型势垒层的晶格常数小的晶格常数的第一层（层）的层叠层和具有比p型阻挡层的晶格常数小的第二层（b层） 大于第一层的晶格常数。

公开(公告)号：US20140110758A1

公开(公告)日：2014-04-24

申请号：US14124600

申请日：2011-06-08

申请人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

发明人： Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Makoto Kiyama

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/66431 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8128

摘要： The semiconductor device is formed in the form of a GaN-based stacked layer including an n-type drift layer 4, a p-type layer 6, and an n-type top layer 8. The semiconductor device includes a regrown layer 27 formed so as to cover a portion of the GaN-based stacked layer that is exposed to an opening 28, the regrown layer 27 including a channel. The channel is two-dimensional electron gas formed at an interface between the electron drift layer and the electron supply layer. When the electron drift layer 22 is assumed to have a thickness of d, the p-type layer 6 has a thickness in the range of d to 10d, and a graded p-type impurity layer 7 whose concentration decreases from a p-type impurity concentration in the p-type layer is formed so as to extend from a (p-type layer/n-type top layer) interface to the inside of the n-type top layer.

摘要翻译： 半导体器件形成为包括n型漂移层4，p型层6和n型顶层8的GaN基叠层的形式。半导体器件包括如下形成的再生长层27 为了覆盖暴露于开口28的GaN基叠层的一部分，再生长层27包括沟道。 通道是在电子漂移层和电子供给层之间的界面处形成的二维电子气。 当假定电子漂移层22的厚度为d时，p型层6的厚度在d至10d的范围内，并且p型杂质层7的浓度从p型杂质降低 从（p型层/ n型顶层）界面向n型顶层的内部形成p型层的浓度。

公开(公告)号：US20130221434A1

公开(公告)日：2013-08-29

申请号：US13884229

申请日：2011-10-05

申请人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

发明人： Masaya Okada ,  Makoto Kiyama ,  Yu Saitoh ,  Seiji Yaegashi ,  Mitsunori Yokoyama ,  Kazutaka Inoue

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7789

摘要： It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.

摘要翻译： 本发明的目的是提高具有开口的垂直半导体器件的击穿电压特性，并且在开口中包括由二维电子气形成的沟道。 垂直半导体器件包括具有开口28的GaN基叠层15，GaN基叠层15包括n型GaN基漂移层4 / p型GaN基阻挡层6 / n型GaN- 垂直半导体器件包括覆盖开口的再生长层27，包含电子漂移层22和电子供给层26的再生长层27，源电极S和位于 在再生长层上。 栅电极G覆盖长度对应于p型GaN基阻挡层的厚度的部分，并且终止在壁表面上的位置，该位置远离开口的底部。

公开(公告)号：US20130181255A1

公开(公告)日：2013-07-18

申请号：US13824043

申请日：2011-07-06

申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/778 ,  H01L29/0696 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

摘要： There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.

摘要翻译： 提供了一种垂直GaN基半导体器件，其中可以使用p型GaN势垒层改善导通电阻，同时提高击穿电压特性。 半导体器件包括再生长层27，其包括位于开口28的壁表面上的沟道，其端面被覆盖的p型势垒层6，与p型势垒层接触的源极层7， 位于再生长层上的栅电极G和位于开口周围的源电极S. 在半导体器件中，源极层具有超晶格结构，该超晶格结构由包括具有比p型势垒层的晶格常数小的晶格常数的第一层（层）的层叠层和具有比p型阻挡层的晶格常数小的第二层（b层） 大于第一层的晶格常数。

公开(公告)号：US20130168739A1

公开(公告)日：2013-07-04

申请号：US13824248

申请日：2011-07-06

申请人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

发明人： Makoto Kiyama ,  Yu Saitoh ,  Masaya Okada ,  Masaki Ueno ,  Seiji Yaegashi ,  Kazutaka Inoue ,  Mitsunori Yokoyama

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789

摘要： A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.

摘要翻译： 提供了通过确定地固定p型GaN势垒层的电位可以稳定地提高夹断特性和击穿电压特性的垂直半导体器件。 半导体器件包括具有开口的GaN基层叠层，包含覆盖开口壁面的沟道的再生长层，与源电极欧姆接触的n +型源极，p 位于p型GaN势垒层和n +型源极层之间的p +型GaN基辅助层。 p +型GaN基辅助层和n +型源极层形成隧道结，以将p型GaN阻挡层的电位固定在源极电位。