公开(公告)号：US06960494B2

公开(公告)日：2005-11-01

申请号：US10968890

申请日：2004-10-21

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L21/44

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

公开(公告)号：US06836012B2

公开(公告)日：2004-12-28

申请号：US10108363

申请日：2002-03-29

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L2314

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

摘要翻译： 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。

公开(公告)号：US20050051810A1

公开(公告)日：2005-03-10

申请号：US10968890

申请日：2004-10-21

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L29/768

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

摘要翻译： 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。

公开(公告)号：US07148529B2

公开(公告)日：2006-12-12

申请号：US10101108

申请日：2002-03-20

申请人： Mitsuru Oida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Funakura

发明人： Mitsuru Oida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Funakura

IPC分类号： H01L31/72 ,  H01L27/15 ,  H01L29/788 ,  H01L31/232 ,  H01L29/40

CPC分类号： H01L23/552 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light from passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.

摘要翻译： 半导体封装包括（a）插入件，（b）布线层，其包含彼此相邻形成的导体，间隔不导致导体之间短路，布线层覆盖中介层的给定区域，以阻挡光通过 通过给定区域，（c）覆盖未被布线层覆盖的插入件的无布线区域的遮光层，以阻挡通过无布线区域的光，（d）半导体芯片，电连接到 布线层，和（e）密封布线层，遮光层和半导体芯片的树脂模具。

公开(公告)号：US09362196B2

公开(公告)日：2016-06-07

申请号：US13181737

申请日：2011-07-13

申请人： Keiju Yamada ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

发明人： Keiju Yamada ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

摘要翻译： 根据实施例，半导体封装包括安装在插入板上的半导体芯片，密封半导体芯片的密封剂以及覆盖密封剂的导电屏蔽层和插入板的侧表面的至少一部分。 插入板具有通过绝缘基板的多个通路。 多个通孔的一部分具有暴露于插入板的侧表面并在插入板的厚度方向上切割的切割平面。 通孔的切割平面电连接到导电屏蔽层。

公开(公告)号：US20120001324A1

公开(公告)日：2012-01-05

申请号：US13175247

申请日：2011-07-01

申请人： Hideo AOKI ,  Hideko Mukaida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Watabe

发明人： Hideo AOKI ,  Hideko Mukaida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Watabe

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/85375 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a semiconductor device includes a circuit substrate, and first and second semiconductor chips mounted on it. The first semiconductor chip and the second semiconductor chip are flip-chip connected, and an underfill resin is filled between them. The underfill resin has a fillet portion. A thickness T1 of the first semiconductor chip and a thickness T2 of the second semiconductor chip satisfy a relationship of T1/(T1+T2)≦0.6.

摘要翻译： 在一个实施例中，半导体器件包括电路基板，以及安装在其上的第一和第二半导体芯片。 第一半导体芯片和第二半导体芯片被倒装连接，并且在它们之间填充底部填充树脂。 底部填充树脂具有圆角部分。 第一半导体芯片的厚度T1和第二半导体芯片的厚度T2满足T1 /（T1 + T2）＆nlE; 0.6的关系。

公开(公告)号：US08409919B2

公开(公告)日：2013-04-02

申请号：US12882673

申请日：2010-09-15

申请人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

发明人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

IPC分类号： H01L21/60

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7592 ,  H01L2224/81065 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00

摘要： According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.

摘要翻译： 根据一个实施例的制造方法，将第一焊料凸块和第二焊料凸块对齐并且彼此接触放置，然后将第一和第二焊料凸块加热至等于或高于 焊料凸起并熔化，由此形成第一焊料凸块和第二焊料凸块的部分连接体。 部分连接体被冷却。 冷却的部分连接体在还原气氛中被加热到等于或高于焊料凸点的熔点的温度，从而通过熔化部分连接体而形成永久性连接体，同时除去存在于表面上的氧化膜 部分连接体。

公开(公告)号：US20120015687A1

公开(公告)日：2012-01-19

申请号：US13181737

申请日：2011-07-13

申请人： Keiju YAMADA ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

发明人： Keiju YAMADA ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

IPC分类号： H04W88/02 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

摘要翻译： 根据实施例，半导体封装包括安装在插入板上的半导体芯片，密封半导体芯片的密封剂以及覆盖密封剂的导电屏蔽层和插入板的侧表面的至少一部分。 插入板具有通过绝缘基板的多个通路。 多个通孔的一部分具有暴露于插入板的侧表面并在插入板的厚度方向上切割的切割平面。 通孔的切割平面电连接到导电屏蔽层。

公开(公告)号：US20110076801A1

公开(公告)日：2011-03-31

申请号：US12882673

申请日：2010-09-15

申请人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

发明人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

IPC分类号： H01L21/60

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7592 ,  H01L2224/81065 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00

摘要： According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.

摘要翻译： 根据一个实施例的制造方法，将第一焊料凸块和第二焊料凸块对齐并且彼此接触放置，然后将第一和第二焊料凸块加热至等于或高于 焊料凸起并熔化，由此形成第一焊料凸块和第二焊料凸块的部分连接体。 部分连接体被冷却。 冷却的部分连接体在还原气氛中被加热到等于或高于焊料凸点的熔点的温度，从而通过熔化部分连接体而形成永久性连接体，同时除去存在于表面上的氧化膜 部分连接体。

公开(公告)号：US20060060912A1

公开(公告)日：2006-03-23

申请号：US11247328

申请日：2005-10-12

申请人： Masaki Ishidao ,  Masahiro Kobayashi ,  Masatoshi Fukuda

发明人： Masaki Ishidao ,  Masahiro Kobayashi ,  Masatoshi Fukuda

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C16/0475 ,  H01L29/7887

摘要： A polysilicon film and the like are patterned to form n-diffusion layers on a silicon substrate. Subsequently, an outer edge of an Al2O3 film is made retreat to be smaller than that of a gate electrode by performing isotropic etching of the Al2O3 film, using a solution of sulfuric acid with hydrogen peroxide. A silicon oxide film, a silicon nitride film, the polysilicon film and the like are hardly removed although the solution of sulfuric acid with hydrogen peroxide exhibits higher etching rate to the Al2O3 film, enabling almost exclusive etching of the Al2O3 film at a high selectivity ratio. Subsequently, another polysilicon film is formed so as to fill spaces formed after the retreat of the Al2O3 film under the silicon oxide film. Subsequently, a sidewall insulating film is formed by remaining portions of the later polysilicon film in the spaces by performing RIE, oxidation, or the like of the later polysilicon film.

摘要翻译： 图案化多晶硅膜等，以在硅衬底上形成n扩散层。 随后，通过对Al 2 O 3膜进行各向同性蚀刻，使Al 2 O 3膜的外边缘退回到小于栅电极的外边缘， 使用硫酸与过氧化氢的溶液进行反应。 尽管硫酸与过氧化氢的溶液表现出较高的蚀刻速率，但是Al 2 O 3 O 3不能除去氧化硅膜，氮化硅膜，多晶硅膜等， SUB>膜，使得能够以高选择比几乎独特地蚀刻Al 2 O 3膜。 随后，形成另外的多晶硅膜，以填充氧化硅膜下的Al 2 O 3 N 3膜后退形成的空间。 随后，通过进行稍后多晶硅膜的RIE，氧化等，在剩余的多晶硅膜的剩余部分中形成侧壁绝缘膜。