公开(公告)号：US09362196B2

公开(公告)日：2016-06-07

申请号：US13181737

申请日：2011-07-13

申请人： Keiju Yamada ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

发明人： Keiju Yamada ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

IPC分类号： H01L23/02 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

摘要翻译： 根据实施例，半导体封装包括安装在插入板上的半导体芯片，密封半导体芯片的密封剂以及覆盖密封剂的导电屏蔽层和插入板的侧表面的至少一部分。 插入板具有通过绝缘基板的多个通路。 多个通孔的一部分具有暴露于插入板的侧表面并在插入板的厚度方向上切割的切割平面。 通孔的切割平面电连接到导电屏蔽层。

公开(公告)号：US20120001324A1

公开(公告)日：2012-01-05

申请号：US13175247

申请日：2011-07-01

申请人： Hideo AOKI ,  Hideko Mukaida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Watabe

发明人： Hideo AOKI ,  Hideko Mukaida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Watabe

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/85375 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a semiconductor device includes a circuit substrate, and first and second semiconductor chips mounted on it. The first semiconductor chip and the second semiconductor chip are flip-chip connected, and an underfill resin is filled between them. The underfill resin has a fillet portion. A thickness T1 of the first semiconductor chip and a thickness T2 of the second semiconductor chip satisfy a relationship of T1/(T1+T2)≦0.6.

摘要翻译： 在一个实施例中，半导体器件包括电路基板，以及安装在其上的第一和第二半导体芯片。 第一半导体芯片和第二半导体芯片被倒装连接，并且在它们之间填充底部填充树脂。 底部填充树脂具有圆角部分。 第一半导体芯片的厚度T1和第二半导体芯片的厚度T2满足T1 /（T1 + T2）＆nlE; 0.6的关系。

公开(公告)号：US06198161B1

公开(公告)日：2001-03-06

申请号：US09391660

申请日：1999-09-07

申请人： Yasuhiro Koshio

发明人： Yasuhiro Koshio

IPC分类号： H01L2300

CPC分类号： H01L24/10 ,  H01L23/3107 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/90 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81899 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19042 ,  H05K3/326 ,  H01L2924/00012 ,  H01L2924/00

摘要： This semiconductor device comprises a semiconductor package having a first wiring substrate and a semiconductor element disposed or mounted thereon, a mounting second wiring substrate, and a protrusion electrode terminal and a receiving terminal portion for connecting an external connecting terminal of the semiconductor package and an external connecting terminal of the second mounting wiring substrate. The protrusion electrode terminal coated with a conductor layer is disposed on the external connecting terminal of the semiconductor package. An aggregated electrode layer having a plurality of fiber electrodes that are bound or tangled is disposed on the external connecting terminal of the mounting wiring substrate. The protrusion electrode terminal on the semiconductor package side is detachably inserted into the aggregated electrode layer on the mounting wiring substrate side. Thus, the protrusion electrode terminal and the aggregated electrode layer are mechanically secured and electrically connected. Consequently, the semiconductor device has high mounting reliability without need to use solder. Thus, the cost of the material of the semiconductor device can be reduced and the number of fabrication steps thereof can be decreased.

摘要翻译： 该半导体器件包括具有第一布线基板和设置或安装在其上的半导体元件的半导体封装，安装第二布线基板和突起电极端子以及用于连接半导体封装的外部连接端子和外部连接端子的接收端子部分 第二安装布线基板的连接端子。 涂覆有导体层的突起电极端子设置在半导体封装的外部连接端子上。 具有多个结合或缠结的纤维电极的聚集电极层设置在安装布线基板的外部连接端子上。 半导体封装侧的突出电极端子可拆卸地插入到安装布线基板侧的聚集电极层中。 因此，突起电极端子和聚集电极层被机械地固定和电连接。 因此，半导体器件具有高的安装可靠性，而不需要使用焊料。 因此，可以降低半导体器件的材料的成本，并且可以减少其制造步骤的数量。

公开(公告)号：US20050051810A1

公开(公告)日：2005-03-10

申请号：US10968890

申请日：2004-10-21

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L29/768

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

摘要翻译： 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。

公开(公告)号：US06551854B2

公开(公告)日：2003-04-22

申请号：US09813160

申请日：2001-03-21

申请人： Eiichi Hosomi ,  Yasuhiro Koshio

发明人： Eiichi Hosomi ,  Yasuhiro Koshio

IPC分类号： H01L2144

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device includes a bonding layer which consists of an intermetallic compound and is positioned between a first electrode and a bump electrode. The bump electrode is mainly made of Au. The intermetallic compound of the bonding layer consist of Au of the bump electrode and a low melting metal.

摘要翻译： 半导体器件包括由金属间化合物组成并且位于第一电极和凸块电极之间的接合层。 凸块电极主要由Au制成。 接合层的金属间化合物由凸起电极的Au和低熔点金属组成。

公开(公告)号：US20120015687A1

公开(公告)日：2012-01-19

申请号：US13181737

申请日：2011-07-13

申请人： Keiju YAMADA ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

发明人： Keiju YAMADA ,  Takashi Yamazaki ,  Masatoshi Fukuda ,  Yasuhiro Koshio

IPC分类号： H04W88/02 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

摘要翻译： 根据实施例，半导体封装包括安装在插入板上的半导体芯片，密封半导体芯片的密封剂以及覆盖密封剂的导电屏蔽层和插入板的侧表面的至少一部分。 插入板具有通过绝缘基板的多个通路。 多个通孔的一部分具有暴露于插入板的侧表面并在插入板的厚度方向上切割的切割平面。 通孔的切割平面电连接到导电屏蔽层。

公开(公告)号：US20110076801A1

公开(公告)日：2011-03-31

申请号：US12882673

申请日：2010-09-15

申请人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

发明人： Hideo Aoki ,  Masatoshi Fukuda ,  Kanako Sawada ,  Yasuhiro Koshio

IPC分类号： H01L21/60

CPC分类号： H01L24/81 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7592 ,  H01L2224/81065 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00

摘要： According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.

摘要翻译： 根据一个实施例的制造方法，将第一焊料凸块和第二焊料凸块对齐并且彼此接触放置，然后将第一和第二焊料凸块加热至等于或高于 焊料凸起并熔化，由此形成第一焊料凸块和第二焊料凸块的部分连接体。 部分连接体被冷却。 冷却的部分连接体在还原气氛中被加热到等于或高于焊料凸点的熔点的温度，从而通过熔化部分连接体而形成永久性连接体，同时除去存在于表面上的氧化膜 部分连接体。

公开(公告)号：US07148529B2

公开(公告)日：2006-12-12

申请号：US10101108

申请日：2002-03-20

申请人： Mitsuru Oida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Funakura

发明人： Mitsuru Oida ,  Masatoshi Fukuda ,  Yasuhiro Koshio ,  Hiroshi Funakura

IPC分类号： H01L31/72 ,  H01L27/15 ,  H01L29/788 ,  H01L31/232 ,  H01L29/40

CPC分类号： H01L23/552 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light from passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.

摘要翻译： 半导体封装包括（a）插入件，（b）布线层，其包含彼此相邻形成的导体，间隔不导致导体之间短路，布线层覆盖中介层的给定区域，以阻挡光通过 通过给定区域，（c）覆盖未被布线层覆盖的插入件的无布线区域的遮光层，以阻挡通过无布线区域的光，（d）半导体芯片，电连接到 布线层，和（e）密封布线层，遮光层和半导体芯片的树脂模具。

公开(公告)号：US06960494B2

公开(公告)日：2005-11-01

申请号：US10968890

申请日：2004-10-21

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L21/44

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

公开(公告)号：US06836012B2

公开(公告)日：2004-12-28

申请号：US10108363

申请日：2002-03-29

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L2314

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

摘要翻译： 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。