-
公开(公告)号：US20240341034A1
公开(公告)日：2024-10-10
申请号：US18623091
申请日：2024-04-01
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Susumu KAGOHASHI
CPC classification number: H05K1/116 , H05K1/0242 , H05K1/09 , H05K3/002 , H05K3/0035 , H05K3/0041 , H05K3/108 , H05K3/423 , H05K1/0306 , H05K1/0373 , H05K2201/0209 , H05K2201/0338 , H05K2201/096 , H05K2203/0723
Abstract: A wiring substrate includes a core substrate having a through-hole conductor, a resin insulating layer formed on the core substrate, a conductor layer formed on the insulating layer and including a seed layer and an electrolytic plating layer, and a via conductor formed in the insulating layer. The via conductor electrically connects the through-hole conductor and conductor layer. The via conductor includes the seed layer and electrolytic plating layer extending from the conductor layer. The core substrate includes a glass substrate and has a through hole penetrating through the glass substrate. The through-hole conductor is formed in the through hole. The seed layer is covering inner wall surface of the insulating layer in opening in which the via conductor is formed. The seed layer has a first portion and a second portion electrically connected to the first portion. That part of the first portion is formed on the second portion.
-
公开(公告)号：US20240341033A1
公开(公告)日：2024-10-10
申请号：US18625662
申请日：2024-04-03
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Susumu KAGOHASHI
CPC classification number: H05K1/115 , H05K3/4038 , H05K2201/0245 , H05K2201/096 , H05K2201/09827 , H05K2201/09845 , H05K2203/06
Abstract: A wiring substrate includes a first build-up part including first insulating and conductor layers, and via conductors, and a second build-up part including second insulating and conductor layers. The first build-up part is laminated on the second build-up part. The minimum wiring width of wirings in the first conductor layers is smaller than the minimum wiring width of wirings in the second conductor layers. The minimum inter-wiring distance of the wirings in the first conductor layers is smaller than the minimum inter-wiring distance of the wirings in the second conductor layers. The first conductor layers and via conductors include a first layer and a second layer. The first layer of each via conductor is covering inner wall surface in a via opening and has a first portion and a second portion. The first portion has a portion formed closer to the center of the via opening than the second portion.
-
公开(公告)号：US20240268038A1
公开(公告)日：2024-08-08
申请号：US18434888
申请日：2024-02-07
Applicant: IBIDEN CO., LTD.
Inventor： Susumu KAGOHASHI , Jun SAKAI , Kyohei YOSHIKAWA
CPC classification number: H05K3/4688 , H05K1/0306 , H05K1/0353 , H05K1/09 , H05K3/4038 , H05K3/423 , H05K2201/0209 , H05K2201/0212 , H05K2201/0323 , H05K2201/0326
Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer including glass particles and resin, a second conductor layer formed on a surface of the resin insulating layer and including a seed layer and an electrolytic plating layer, and a via conductor connecting the first conductor layer and second conductor layer and including the seed layer and electrolytic plating layer extending from the second conductor layer. The second conductor layer and the via conductor are formed such that the second conductor layer includes signal wirings and that the seed layer is formed by sputtering an alloy including copper, aluminum, and one or more metals selected from nickel, zinc, gallium, silicon, and magnesium, and the resin insulating layer is formed such that the surface of the resin insulating layer includes the resin and that an inner wall surface in the opening includes the resin and the glass particles.
-
公开(公告)号：US20240107685A1
公开(公告)日：2024-03-28
申请号：US18475288
申请日：2023-09-27
Applicant: IBIDEN CO., LTD.
Inventor： Susumu KAGOHASHI , Jun SAKAI , Kyohei YOSHIKAWA , Takuya INISHI
CPC classification number: H05K3/4688 , H05K1/0306 , H05K1/0313 , H05K1/116 , H05K3/062 , H05K3/16 , H05K3/4608 , H05K2201/0209 , H05K2201/0212 , H05K2201/0338 , H05K2203/0369
Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed layer and the electrolytic plating layer and connecting the first conductor and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second portion and the third portion, the second portion has a first film and a second film electrically connected to the first film, and a portion of the first film is formed on the second film.
-
公开(公告)号：US20250048562A1
公开(公告)日：2025-02-06
申请号：US18789154
申请日：2024-07-30
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Susumu KAGOHASHI , Jun SAKAI , Kyohei YOSHIKAWA , Takuya INISHI
Abstract: A wiring substrate includes a core substrate including a glass substrate and a through-hole conductor, a resin insulating layer having an opening extending through the resin insulating layer, a conductor layer including a seed layer and an electrolytic plating layer on the seed layer, and a via conductor formed in the opening such that the via conductor electrically connects to the through-hole conductor in the core substrate and includes the seed layer and electrolytic plating layer extending from the conductor layer. The resin insulating layer includes resin and inorganic particles including first and second particles such that the first particles are partially embedded in the resin and that the second particles are embedded in the resin, the first particles have first portions protruding from the resin and second portions embedded in the resin respectively, the surface includes the resin and exposed surfaces of the first portions exposed from the resin.
-
Patent Agency Ranking
公开(公告)号：US20250008652A1
公开(公告)日：2025-01-02
申请号：US18754732
申请日：2024-06-26
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Susumu KAGOHASHI , Jun SAKAI , Kyohei YOSHIKAWA
Abstract: A printed wiring board includes a first insulating layer, a connection conductor having a connection wiring, a second insulating layer formed on the connection conductor layer, a mounting conductor layer including a first electrode that mounts a first electronic component and a second electrode that mounts a second electronic component, and connection via conductors including a first connection via conductor that electrically connects the first electrode and the connection wiring and a second connection via conductor that electrically connects the second electrode and the connection wiring. The first insulating layer includes resin and inorganic particles including first particles and second particles such that each first particle has a first portion protruding from the resin and a second portion embedded in the resin, and the surface of the first insulating layer includes a surface of the resin and exposed surfaces of the first portions exposed from the surface of the resin.
-
公开(公告)号：US20240339393A1
公开(公告)日：2024-10-10
申请号：US18626395
申请日：2024-04-04
Applicant: IBIDEN CO., LTD.
Inventor： Masashi KUWABARA , Susumu KAGOHASHI
IPC: H01L23/498 , H01L21/48 , H01L21/683
CPC classification number: H01L23/49838 , H01L21/4857 , H01L23/49822 , H01L21/6835 , H01L2221/68345
Abstract: A wiring substrate includes a first build-up part including first insulating and conductor layers, and via conductors, and a second build-up part including second insulating and conductor layers. The minimum wiring width in the first conductor layers is smaller than the minimum wiring width in the second conductor layers. The minimum inter-wiring distance in the first conductor layers is smaller than the minimum inter-wiring distance in the second conductor layers. Each first conductor layer and each via conductor include first and second layers. The first layer includes a first portion covering respective surface of the first insulating layers, a second portion covering inner wall surface in respective via opening in the first insulating layers, and a third portion covering bottom surface in the respective via opening. The thickness of the first portion is larger than the thickness of the second portion and larger than the thickness of the third portion.
-
公开(公告)号：US20240268021A1
公开(公告)日：2024-08-08
申请号：US18434910
申请日：2024-02-07
Applicant: IBIDEN CO., LTD.
Inventor： Susumu KAGOHASHI , Kiyohiro ISHIKAWA
CPC classification number: H05K1/05 , H05K1/0298 , H05K1/115 , H05K3/16 , H05K2201/0209 , H05K2201/0242 , H05K2203/0723
Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer including inorganic particles and resin, a second conductor layer including a seed layer and an electrolytic plating layer, and a via conductor connecting the first conductor layer and second conductor layer and including the seed layer and electrolytic plating layer extending from the second conductor layer. The inorganic particles include first particles, second particles, third particles and fourth particles formed such that the first and second particles are solid particles, the third and fourth particles are hollow particles, the first and third particles form an inner wall surface of the opening in the resin insulating layer, the second and fourth particles are embedded in the resin insulating layer, the first particles have shapes that are different from shapes of the second particles, and the third particles have shapes that are different from shapes of the fourth particles.
-
公开(公告)号：US20240179853A1
公开(公告)日：2024-05-30
申请号：US18519524
申请日：2023-11-27
Applicant: IBIDEN CO., LTD.
Inventor： Susumu KAGOHASHI , Jun SAKAI
CPC classification number: H05K3/4605 , H05K1/0306 , H05K3/108 , H05K3/423
Abstract: A wiring substrate includes an insulating layer including inorganic particles and resin, a seed layer formed on a surface of the insulating layer, and a conductor layer including a conductor pattern and formed on the seed layer. The surface of the insulating layer is a roughened surface formed such that the roughened surface of the insulating layer has exposed portions of the inorganic particles and resin with gaps at interfaces where the inorganic particles and the resin are in contact, and the seed layer is formed on the roughened surface of the insulating layer such that the seed layer is formed along the exposed portions of the inorganic particles and resin exposed on the roughened surface of the insulating layer and is not formed in the gaps at the interfaces where the inorganic particles and the resin are in contact.
-
公开(公告)号：US20230328882A1
公开(公告)日：2023-10-12
申请号：US18191033
申请日：2023-03-28
Applicant: IBIDEN CO., LTD.
Inventor： Susumu KAGOHASHI
CPC classification number: H05K1/0298 , H05K1/115 , H05K3/423 , H05K2201/09845
Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the resin insulating layer, and a via conductor formed in an opening formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer. The via conductor is formed such that the via conductor includes a seed layer covering an inner wall surface of the resin insulating layer inside of the opening and an electrolytic plating layer formed on the seed layer such that the seed layer has a plurality of columnar parts grown in columnar shapes.
-
-
-
-
-
-
-
-
-
Search Results
26
records
(took 0.019 seconds)
