公开(公告)号：US20200006643A1

公开(公告)日：2020-01-02

申请号：US16024712

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Gary ALLEN ,  Scott B. CLENDENING ,  Ian YOUNG

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L27/22

Abstract: Embodiments herein relate to manufacturing a magnetic random access memory (MRAM). In particular, a process may include coupling a side of a magnetic free layer of a magnetic tunnel junction (MTJ) to a first side of a hybrid spin orbit torque (SOT) electrode-insert layer, coupling a first side of an atomic layer etching (ALE) etch layer to a second side of the hybrid SOT electrode-insert layer opposite the first side, applying an interlayer dielectric (ILD) layer to edges of the MTJ, the SOT electrode and the etch layers, the ILD layer in a plane substantially perpendicular to a plane of the MTJ, SOT electrode and ALE etch layers, and etching the ALE etch layer using ALE until the SOT layer is exposed.

公开(公告)号：US20200006636A1

公开(公告)日：2020-01-02

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Gary ALLEN ,  Kaan OGUZ ,  Kevin O?BRIEN ,  Noriyuki SATO ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US20200313075A1

公开(公告)日：2020-10-01

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Kevin O'Brien ,  Benjamin BUFORD ,  Tofizur RAHMAN ,  Rohan PATIL ,  Nafees KABIR ,  Michael CHRISTENSON ,  Ian YOUNG ,  Hui Jae YOO ,  Christopher WIEGAND

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US20200312978A1

公开(公告)日：2020-10-01

申请号：US16363952

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jack KAVALIEROS ,  Ian YOUNG ,  Matthew METZ ,  Uygar AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Seung Hoon SUNG ,  Aditya KASUKURTI ,  Sou-Chi CHANG ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  G09G3/36 ,  G02F1/141 ,  H01L21/28

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

公开(公告)号：US20200227105A1

公开(公告)日：2020-07-16

申请号：US16246362

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Ian YOUNG

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02

Abstract: A memory device includes a spin orbit electrode structure having a dielectric structure including a first sidewall, a second sidewall opposite to the first sidewall, a top surface. The spin orbit electrode structure further includes an electrode having a spin orbit material adjacent to the dielectric structure, where the electrode has a first electrode portion on the top surface, a second electrode portion adjacent to the first sidewall and a third electrode portion adjacent to the second sidewall. The first electrode portion, the second electrode portion and the third electrode portion are contiguous. The spin orbit electrode structure further includes a conductive interconnect in contact with the second electrode portion or the third electrode portion. The memory device further includes a magnetic junction device on a portion of the top surface of the first electrode portion.

公开(公告)号：US20200006637A1

公开(公告)日：2020-01-02

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Kaan OGUZ ,  Christopher WIEGAND ,  Angeline SMITH ,  Noriyuki SATO ,  Kevin O'BRIEN ,  Benjamin BUFORD ,  Ian YOUNG ,  MD Tofizur RAHMAN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20200006627A1

公开(公告)日：2020-01-02

申请号：US16022519

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12

Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

公开(公告)号：US20190189173A1

公开(公告)日：2019-06-20

申请号：US16326308

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sasikanth MANIPATRUNI ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: G11C11/16 ,  H03K19/16 ,  H01L29/66 ,  H01L29/82 ,  H03K19/18

CPC classification number: G11C11/161 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/06 ,  H03K19/16 ,  H03K19/18

Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

公开(公告)号：US20190013063A1

公开(公告)日：2019-01-10

申请号：US16079400

申请日：2016-03-23

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Sasikanth MANIPATRUNI ,  Daniel H. MORRIS ,  Kaushik VAIDYANATHAN ,  Niloy MUKHERJEE ,  Dmitri E. NIKONOV ,  Ian YOUNG ,  Tanay KARNIK

IPC: G11C11/413 ,  G11C11/412 ,  G11C13/00 ,  G11C14/00 ,  G11C7/10

CPC classification number: G11C11/413 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/20 ,  G11C11/412 ,  G11C13/0007 ,  G11C14/009 ,  G11C2213/70 ,  G11C2213/71

Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

公开(公告)号：US20220140230A1

公开(公告)日：2022-05-05

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Chia-Ching LIN ,  Christopher WIEGAND ,  Tanay GOSAVI ,  Ian YOUNG

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H01L27/22

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.