公开(公告)号：US20200212055A1

公开(公告)日：2020-07-02

申请号：US16236047

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sasikanth MANIPATRUNI ,  Tanay GOSAVI ,  Dmitri NIKONOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: H01L27/11507

Abstract: A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer.

公开(公告)号：US20200006636A1

公开(公告)日：2020-01-02

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Gary ALLEN ,  Kaan OGUZ ,  Kevin O?BRIEN ,  Noriyuki SATO ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US20190138893A1

公开(公告)日：2019-05-09

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Uygar AVCI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL ,  Nazila HARATIPOUR ,  Van H. LE

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20190042199A1

公开(公告)日：2019-02-07

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin SUMBUL ,  Phil KNAG ,  Gregory K. CHEN ,  Raghavan KUMAR ,  Abhishek SHARMA ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Ram KRISHNAMURTHY ,  Ian A. YOUNG

IPC: G06F7/544 ,  G11C8/10 ,  G11C7/12 ,  G11C8/08 ,  G06N3/08

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US20170345496A1

公开(公告)日：2017-11-30

申请号：US15164665

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Huichu LIU ,  Daniel H. MORRIS ,  Sasikanth MANIPATRUNI ,  Kaushik VAIDYANATHAN ,  Ian A. YOUNG ,  Tanay KARNIK

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

Abstract: An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to be coupled to the select line during a first mode and to be de-coupled during a second mode.

公开(公告)号：US20200006643A1

公开(公告)日：2020-01-02

申请号：US16024712

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Chia-Ching LIN ,  Gary ALLEN ,  Scott B. CLENDENING ,  Ian YOUNG

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L27/22

Abstract: Embodiments herein relate to manufacturing a magnetic random access memory (MRAM). In particular, a process may include coupling a side of a magnetic free layer of a magnetic tunnel junction (MTJ) to a first side of a hybrid spin orbit torque (SOT) electrode-insert layer, coupling a first side of an atomic layer etching (ALE) etch layer to a second side of the hybrid SOT electrode-insert layer opposite the first side, applying an interlayer dielectric (ILD) layer to edges of the MTJ, the SOT electrode and the etch layers, the ILD layer in a plane substantially perpendicular to a plane of the MTJ, SOT electrode and ALE etch layers, and etching the ALE etch layer using ALE until the SOT layer is exposed.

公开(公告)号：US20190065151A1

公开(公告)日：2019-02-28

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. CHEN ,  Raghavan KUMAR ,  Huseyin Ekin SUMBUL ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Ian A. YOUNG

IPC: G06F7/544 ,  G06F9/30 ,  G06F7/501 ,  G06F17/16

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit x n-bit multiplications.

公开(公告)号：US20190042949A1

公开(公告)日：2019-02-07

申请号：US16147143

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. YOUNG ,  Ram KRISHNAMURTHY ,  Sasikanth MANIPATRUNI ,  Gregory K. CHEN ,  Amrita MATHURIYA ,  Abhishek SHARMA ,  Raghavan KUMAR ,  Phil KNAG ,  Huseyin Ekin SUMBUL

IPC: G06N3/10 ,  G06F17/50 ,  G06N3/063

Abstract: A semiconductor chip is described. The semiconductor chip includes a compute-in-memory (CIM) circuit to implement a neural network in hardware. The semiconductor chip also includes at least one output that presents samples of voltages generated at a node of the CIM circuit in response to a range of neural network input values applied to the CIM circuit to optimize the CIM circuit for the neural network.

公开(公告)号：US20180158588A1

公开(公告)日：2018-06-07

申请号：US15569978

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth MANIPATRUNI ,  Anurag CHAUDHRY ,  Dmitri E. NIKONOV ,  Ian A. YOUNG

IPC: H01F10/32 ,  H01L43/10 ,  G11C11/16 ,  G11C11/155 ,  H03K19/16 ,  H01L43/08

CPC classification number: H01F10/3268 ,  G11C11/155 ,  G11C11/1675 ,  H01F10/265 ,  H01L43/08 ,  H01L43/10 ,  H03K19/16 ,  H03K19/18

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

公开(公告)号：US20160300612A1

公开(公告)日：2016-10-13

申请号：US15036761

申请日：2013-12-24

Applicant: Sasikanth MANIPATRUNI ,  Ian A. YOUNG ,  INTEL CORPORATION

Inventor： Sasikanth MANIPATRUNI ,  Ian A. YOUNG

IPC: G11C14/00 ,  G11C11/16 ,  H01L27/108 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C13/00 ,  H01L27/22

CPC classification number: G11C14/0036 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0069 ,  G11C14/0018 ,  G11C14/0045 ,  H01L27/10832 ,  H01L27/1087 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H04L9/0897

Abstract: Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor having a gate terminal coupled to a first word line (WL), a source/drain terminal coupled to bit line (BL), and drain/source terminal coupled to the first terminal of the capacitor; a resistive memory element having a first terminal and a second terminal, the first terminal of the resistive memory element device coupled to the first terminal of the capacitor; and a second transistor having a gate terminal coupled to a second WL, a source/drain terminal coupled to source line (SL), and drain/source terminal coupled to the second terminal of the resistive memory element device.

Abstract translation: 描述了一种用于混合eDRAM和MRAM存储单元的装置，包括：具有第一端子和第二端子的电容器; 第一晶体管，其具有耦合到第一字线（WL）的栅极端子，耦合到位线（BL）的源极/漏极端子以及耦合到所述电容器的所述第一端子的漏极/源极端子; 具有第一端子和第二端子的电阻性存储元件，所述电阻式存储元件器件的所述第一端子耦合到所述电容器的第一端子; 以及第二晶体管，其具有耦合到第二WL的栅极端子，耦合到源极线（SL）的源极/漏极端子以及耦合到所述电阻性存储器件器件的所述第二端子的漏极/源极端子。