公开(公告)号：US10580926B2

公开(公告)日：2020-03-03

申请号：US15296269

申请日：2016-10-18

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Bahman Hekmatshoartabari ,  Davood Shahrjerdi

IPC: H01L31/18 ,  H01L31/0376 ,  H01L31/078 ,  H01L31/028 ,  H01L31/0368 ,  H01L27/142 ,  H01L31/0687

Abstract: A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

公开(公告)号：US09397226B2

公开(公告)日：2016-07-19

申请号：US14938904

申请日：2015-11-12

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Cheng-Wei Cheng ,  Wilfried E. Haensch ,  Amlan Majumdar ,  Kuen-Ting Shiu

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/152 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78642

Abstract: An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.

Abstract translation: 形成具有受控栅极重叠的垂直场效应晶体管的半导体结构的方法。 该方法包括在半导体衬底上形成第一半导体层，第二半导体层，第三半导体层，第四半导体层，第五半导体层和第一电介质层。 蚀刻的第一介电层和第一漏极接触被第一间隔物包围。 第一漏极接触由第五半导体层构成。 形成由第四半导体层，由第三半导体层构成的沟道和由第二半导体层构成的第二源极触点构成的第二漏极接触。 此外，形成由第一半导体构成的第一源极接触，并且在围绕第一柱和第二柱的一部分的第一源极接触层的一部分上形成栅电极。

公开(公告)号：US20160204253A1

公开(公告)日：2016-07-14

申请号：US14592130

申请日：2015-01-08

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/7842 ,  H01L29/7849

Abstract: Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.

公开(公告)号：US09368574B1

公开(公告)日：2016-06-14

申请号：US14924782

申请日：2015-10-28

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L21/336 ,  H01L29/775 ,  H01L29/66 ,  H01L21/335 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/0669 ,  H01L21/0259 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7782 ,  H01L29/78696 ,  H01L51/0048

Abstract: A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner gate. The first epitaxial dielectric layer is surrounded by an epitaxial semiconductor channel. The epitaxial semiconductor channel surrounds a second dielectric layer. A gate conductor surrounds the second dielectric layer. The gate conductor is patterned into a gate line and defines a channel region overlapping the gate line. The semiconductor device contains source and drain regions adjacent to the gate line.

公开(公告)号：US20160149020A1

公开(公告)日：2016-05-26

申请号：US14802722

申请日：2015-07-17

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/16 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/66666 ,  H01L29/0603 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/7827 ,  H01L29/78609 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/78696

Abstract: An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

公开(公告)号：US20160048997A1

公开(公告)日：2016-02-18

申请号：US14461766

申请日：2014-08-18

Applicant: International Business Machines Corporation

Inventor： Aleksandr Y. Aravkin ,  Anirban Basu ,  Dimitri Kanevsky ,  Tara N. Sainath

IPC: G06T15/04 ,  G06K9/62 ,  G06T7/00 ,  G06F3/01 ,  G06K9/00

CPC classification number: G06K9/6202 ,  G01B11/30 ,  G06F3/016 ,  G09B21/00

Abstract: Systems and methods for generating a tactile representation of an object are provided. A method for generating a tactile representation of an object, comprises obtaining a microscopic image of a surface of the object, processing data corresponding to the image to generate a roughness pattern for the object based on the image, calibrating the roughness pattern with a predetermined material, and simulating the roughness pattern on an electronic device.

Abstract translation: 提供了用于产生对象的触觉表示的系统和方法。 一种用于生成对象的触觉表示的方法，包括获得对象的表面的显微图像，处理与图像相对应的数据，以基于图像生成对象的粗糙图案，使用预定材料校正粗糙图案 ，并模拟电子设备上的粗糙图案。

公开(公告)号：US09159822B2

公开(公告)日：2015-10-13

申请号：US14187708

申请日：2014-02-24

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Amlan Majumdar ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/8249 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02 ,  H01L21/324 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/28575 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/778 ,  H01L29/7784

Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.

Abstract translation: 一种方法，包括沿着栅极沟槽的垂直侧壁形成一对内部间隔物，延伸到含III-V族化合物半导体的异质结构中的栅极沟槽，在栅极沟槽内形成栅极导体，去除第一介电层选择性的一部分 到栅极导体和一对内部间隔件，形成与该对内部间隔件相邻的一对外部间隔件，外部间隔件与内部间隔件直接接触并与其自对准，并且形成一对源极 -​​ 漏极 在含有III-V族化合物半导体的异质结构的最上层的接触点处，一对源极 -​​ 漏极接触件与该一对外部间隔物自对准，使得每个源极 - 漏极接触部分的边缘与外部边缘 。

公开(公告)号：US09136357B1

公开(公告)日：2015-09-15

申请号：US14197746

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L21/8242 ,  H01L21/00 ,  H01L21/337 ,  H01L21/338 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/205

CPC classification number: H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.

Abstract translation: 一种用于制造多重装置的方法包括在多重装置的衬底上形成翅片，翅片由半导体材料形成，直接在翅片和衬底上生长第一共形外延层，其中第一共形外延层未掺杂或 轻掺杂，直接在第一共形外延层上生长第二共形外延层，其中第二共形外延层是高度掺杂的，选择性地去除第二外延层的一部分以暴露第一共形外延层的一部分，从而形成 沟槽，并在沟槽内形成栅极。

公开(公告)号：US20150248835A1

公开(公告)日：2015-09-03

申请号：US14193750

申请日：2014-02-28

Applicant: International Business Machines Corporation

Inventor： Aleksandr Y. Aravkin ,  Anirban Basu ,  Dimitri Kanevsky ,  Tara N. Sainath ,  Premal Y. Shah

IPC: G08G1/14

CPC classification number: G08G1/14 ,  G01C21/3685 ,  G08G1/04 ,  G08G1/143 ,  G08G1/144 ,  G08G1/146 ,  G08G1/147 ,  G08G1/149

Abstract: Systems and methods for providing a user with information on spaces in which to park a vehicle are provided. A method for providing a user with information on spaces in which to park a vehicle, comprises identifying one or more spaces in which to park the vehicle, selecting valid spaces from the identified one or more spaces based on a validation criteria, and ranking the valid spaces and providing a ranked list of the valid spaces to the user, wherein the identifying, selecting, ranking and providing steps are performed by a computer system comprising a memory and at least one processor coupled to the memory.

Abstract translation: 提供了向用户提供关于停放车辆的空间的信息的系统和方法。 一种用于向用户提供关于停放车辆的空间的信息的方法，包括识别在其中停放车辆的一个或多个空间，基于验证标准从所识别的一个或多个空间中选择有效空间，并将有效的 并且向用户提供有效空间的排名列表，其中识别，选择，排名和提供步骤由包括存储器的计算机系统和耦合到存储器的至少一个处理器执行。

公开(公告)号：US20150061013A1

公开(公告)日：2015-03-05

申请号：US14010585

申请日：2013-08-27

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42356 ,  H01L21/28026 ,  H01L21/283 ,  H01L29/1054 ,  H01L29/201 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

Abstract translation: 形成跨越半导体鳍片的一次性栅极结构。 使用一次性栅极结构作为注入掩模形成源区和漏区。 形成平坦化介电层，使得平坦化介电层的顶表面与一次性栅极结构共面。 通过去除一次性栅极结构形成栅极腔。 外延盖层通过选择性外延沉积在半导体鳍片的物理暴露的半导体表面上。 在外延盖层上形成栅极电介质层，并且可以通过填充栅极腔来形成栅电极。 外延盖层可以包括降低与栅极介电层的界面处的界面缺陷密度的材料。