公开(公告)号：US09098281B2

公开(公告)日：2015-08-04

申请号：US13980368

申请日：2012-03-08

申请人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

发明人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC分类号： G06F1/04 ,  G06F1/32 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

摘要： An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

摘要翻译： 集成电路包括具有控制定时域和数据定时域的物理层接口，以及响应于第一事件而在功率节省模式改变期间实现控制定时域的电路，并且响应于数据定时域 到第二个事件。 控制定时域可以包括耦合到命令和地址路径的接口电路，并且数据定时域可以包括耦合到数据路径的接口电路。

公开(公告)号：US20130339775A1

公开(公告)日：2013-12-19

申请号：US13980368

申请日：2012-03-08

申请人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

发明人： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC分类号： G06F1/32 ,  G06F1/04

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

摘要： An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20090059642A1

公开(公告)日：2009-03-05

申请号：US12204728

申请日：2008-09-04

申请人： Frederick Ware ,  John Wilson ,  John C. Eble, III ,  Jade M. Kizer ,  Lei Luo ,  John W. Poulton ,  Ian Shaeffer

发明人： Frederick Ware ,  John Wilson ,  John C. Eble, III ,  Jade M. Kizer ,  Lei Luo ,  John W. Poulton ,  Ian Shaeffer

IPC分类号： G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/147

摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.

摘要翻译： 存储器控制器以两种模式操作以支持不同类型的存储器件。 在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。 参考电压使用可替换地用于例如电极的焊盘传送。 定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

公开(公告)号：US09412428B2

公开(公告)日：2016-08-09

申请号：US14003722

申请日：2012-03-21

申请人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

发明人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC分类号： G06F12/00 ,  G11C7/22 ,  G11C29/02

CPC分类号： G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

摘要翻译： 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：US20130346721A1

公开(公告)日：2013-12-26

申请号：US14003722

申请日：2012-03-21

申请人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

发明人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC分类号： G11C7/22

CPC分类号： G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

摘要翻译： 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：US08068357B2

公开(公告)日：2011-11-29

申请号：US12204728

申请日：2008-09-04

申请人： Frederick Ware ,  John Wilson ,  John C. Eble, III ,  Jade M. Kizer ,  Lei Luo ,  John W. Poulton ,  Ian Shaeffer

发明人： Frederick Ware ,  John Wilson ,  John C. Eble, III ,  Jade M. Kizer ,  Lei Luo ,  John W. Poulton ,  Ian Shaeffer

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C5/147

摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.

摘要翻译： 存储器控制器以两种模式操作以支持不同类型的存储器件。 在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。 参考电压使用可替换地用于例如电极的焊盘传送。 定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

公开(公告)号：US10445226B2

公开(公告)日：2019-10-15

申请号：US13814917

申请日：2011-08-04

申请人： Ian Shaeffer ,  Brent S. Haukness

发明人： Ian Shaeffer ,  Brent S. Haukness

IPC分类号： G06F12/00 ,  G11C16/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

摘要： A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

公开(公告)号：US09665507B2

公开(公告)日：2017-05-30

申请号：US13105798

申请日：2011-05-11

申请人： Ian Shaeffer ,  Thomas J. Giovannini

发明人： Ian Shaeffer ,  Thomas J. Giovannini

IPC分类号： G06F13/16 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F13/1689 ,  G06F12/00 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2254

摘要： Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US09263103B2

公开(公告)日：2016-02-16

申请号：US12049928

申请日：2008-03-17

申请人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC分类号： G06F12/00 ,  G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

摘要翻译： 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。 在该系统的变型中，存储器芯片上的相位检测器被配置为从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记特定时钟的脉冲 在时钟信号周期。 在该变型中，相位检测器被配置为使用标记信号来在时钟信号中画出特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生返回到 内存控制器便于校准时序关系。

公开(公告)号：US20150255144A1

公开(公告)日：2015-09-10

申请号：US14698755

申请日：2015-04-28

申请人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

发明人： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC分类号： G11C11/4076 ,  G11C11/409

CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

摘要翻译： 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。