公开(公告)号：US09064862B2

公开(公告)日：2015-06-23

申请号：US13564431

申请日：2012-08-01

申请人： In Chul Hwang ,  Jae Myun Kim ,  Seung Jee Kim ,  Jin Su Lee

发明人： In Chul Hwang ,  Jae Myun Kim ,  Seung Jee Kim ,  Jin Su Lee

IPC分类号： H01L21/50 ,  H01L25/00 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/81191 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/81

摘要： Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.

摘要翻译： 提供双层结构半导体芯片。 半导体芯片包括接合到第一半导体芯片的第一半导体芯片和第二半导体芯片。 第一半导体芯片包括具有第一底表面的第一基板。 第二半导体芯片包括具有第二底面的第二基板。 第一底面直接接触第二底面。 还提供了相关包和相关方法。

公开(公告)号：US08390114B2

公开(公告)日：2013-03-05

申请号：US12835921

申请日：2010-07-14

申请人： Jae Myun Kim ,  Seung Jee Kim ,  Ki Bum Kim

发明人： Jae Myun Kim ,  Seung Jee Kim ,  Ki Bum Kim

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.

摘要翻译： 半导体封装包括衬底，附着到衬底的第一半导体芯片模块，附接到第一半导体芯片模块的导电连接构件和附接到导电连接构件的第二半导体芯片模块。 第一和第二半导体芯片模块形成为具有阶梯形形状并且沿相反方向横向延伸，以便将锯齿形布置在一起。

公开(公告)号：US07989943B2

公开(公告)日：2011-08-02

申请号：US12492224

申请日：2009-06-26

申请人： Seung Jee Kim ,  Jae Myun Kim ,  Kyoung Mo Yang

发明人： Seung Jee Kim ,  Jae Myun Kim ,  Kyoung Mo Yang

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A staircase shaped stacked semiconductor package is presented which includes a substrate, a multiplicity of semiconductor chip modules, a connection member, and conductive members. The substrate has connection pads along an upper surface edge. Each semiconductor chip module includes a first and a second semiconductor chip that oppose each other. The first and second semiconductor chips have respective first and second bonding pads along exposed surfaces. The connection member is placed on an uppermost semiconductor chip module and has first and second terminals electrically connected to the first and second bonding pads via conductive members. The conductive members are also coupled to the connection pads of the substrate.

摘要翻译： 本发明提供了一种阶梯形叠层半导体封装件，其包括基板，多个半导体芯片模块，连接元件和导电元件。 衬底具有沿着上表面边缘的连接焊盘。 每个半导体芯片模块包括彼此相对的第一和第二半导体芯片。 第一和第二半导体芯片沿着暴露的表面具有相应的第一和第二焊盘。 连接构件被放置在最上面的半导体芯片模块上，并且具有经由导电构件电连接到第一和第二接合焊盘的第一和第二端子。 导电构件也耦合到衬底的连接焊盘。

公开(公告)号：US20080116563A1

公开(公告)日：2008-05-22

申请号：US11754492

申请日：2007-05-29

申请人： Han Jun Bae ,  Jae Myun Kim

发明人： Han Jun Bae ,  Jae Myun Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure covering an upper surface of the substrate including a connection region between the bonding pads and the connection pads and the semiconductor chip; a second molding structure formed adjacent to an edge of the lower surface of the substrate; and a plurality of solder balls attached to the respective ball lands of the substrate.

摘要翻译： 半导体封装包括具有多个连接焊盘和多个焊盘的衬底; 半导体芯片，其附接到所述基板的一个表面，并且具有连接到所述基板的各个连接焊盘的多个焊盘; 覆盖所述基板的上表面的第一模制结构，包括所述焊盘与所述连接焊盘和所述半导体芯片之间的连接区域; 与所述基板的下表面的边缘相邻形成的第二模制结构; 以及附接到基板的相应球台的多个焊球。

公开(公告)号：US20060284298A1

公开(公告)日：2006-12-21

申请号：US11302622

申请日：2005-12-14

申请人： Jae Myun Kim ,  Sung Ho Kim ,  Chan Ki Hwang

发明人： Jae Myun Kim ,  Sung Ho Kim ,  Chan Ki Hwang

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06579 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip stack package has semiconductor chips connected to the substrate by the same signal pathway lengths to prevent malfunction of the semiconductor chips. In the chip stack package, first and second semiconductor chips disposed opposite to each other. The first and second semiconductor chips having bonding bumps are bonded to upper and bottom surfaces of the pattern tape. The bonded chips are then bonded to an upper surface of a substrate. The bond fingers of the substrate are in electrical contact with the bond leads of the pattern tape. Ball lands are formed on the bottom surface of the substrate to which solder balls are attached.

摘要翻译： 芯片堆叠封装具有通过相同的信号通路长度连接到衬底的半导体芯片，以防止半导体芯片的故障。 在芯片堆叠封装中，彼此相对布置的第一和第二半导体芯片。 具有接合凸块的第一和第二半导体芯片被结合到图案带的上表面和底表面。 接合的芯片然后结合到基板的上表面。 基板的键合指与图案带的接合引线电接触。 在焊锡球附着的基板的底面形成有球面。

公开(公告)号：US08304879B2

公开(公告)日：2012-11-06

申请号：US12819279

申请日：2010-06-21

申请人： Da Un Nah ,  Jae Myun Kim ,  Tae Hoon Kim ,  Jung Tae Jeong ,  Bok Gyu Min ,  Ki Bum Kim

发明人： Da Un Nah ,  Jae Myun Kim ,  Tae Hoon Kim ,  Jung Tae Jeong ,  Bok Gyu Min ,  Ki Bum Kim

IPC分类号： H01L23/482

CPC分类号： H01L24/73 ,  H01L23/481 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.

摘要翻译： 提出了一种螺旋状梯形堆叠半导体封装。 封装包括半导体芯片模块，基板和连接构件。 半导体芯片模块包括具有芯片选择焊盘和贯通电极的至少两个半导体芯片。 堆叠半导体芯片，使得芯片选择焊盘被暴露，并且堆叠的半导体芯片的贯通电极彼此电连接。 基板具有安装在其上的半导体芯片模块并具有连接焊盘。 连接构件将芯片选择焊盘电连接到相应的连接焊盘。

公开(公告)号：US07759807B2

公开(公告)日：2010-07-20

申请号：US11754492

申请日：2007-05-29

申请人： Han Jun Bae ,  Jae Myun Kim

发明人： Han Jun Bae ,  Jae Myun Kim

IPC分类号： H01L23/29 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure covering an upper surface of the substrate including a connection region between the bonding pads and the connection pads and the semiconductor chip; a second molding structure formed adjacent to an edge of the lower surface of the substrate; and a plurality of solder balls attached to the respective ball lands of the substrate.

摘要翻译： 半导体封装包括具有多个连接焊盘和多个焊盘的衬底; 半导体芯片，其附接到所述基板的一个表面，并且具有连接到所述基板的各个连接焊盘的多个焊盘; 覆盖所述基板的上表面的第一模制结构，包括所述焊盘与所述连接焊盘和所述半导体芯片之间的连接区域; 与所述基板的下表面的边缘相邻形成的第二模制结构; 以及附接到基板的相应球台的多个焊球。

公开(公告)号：US6121682A

公开(公告)日：2000-09-19

申请号：US469131

申请日：1999-12-21

申请人： Jae Myun Kim

发明人： Jae Myun Kim

IPC分类号： H01L23/28 ,  H01L21/98 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107

摘要： Disclosed is a multi-chip package. According to the present invention, a first semiconductor chip includes a first face in which a bonding pad disposed, and a second face opposite to the first face. A first insulating layer is coated over the first face of the first semiconductor chip so as to expose the bonding pad. A metal pattern is deposited on the first insulating layer and one end of the metal pattern is connected to the exposed bonding pad. A second insulating layer having a via hole exposing the metal pattern and a ball land, is coated over the first face of the first semiconductor chip. A second semiconductor chip includes a first face in which a bonding pad is disposed and opposite to the first face of the first semiconductor chip, and a second face opposite to the first face of the second semiconductor chip. The second semiconductor chip is opposed from the first face of the first semiconductor chip by a selected distance. A third insulating layer is coated on the first face of the second semiconduuctor chip so as to expose the bonding pad of the second semiconductor chip. A conductive bump is formed at the bonding pad of the second semiconductor chip. The conductive bump is inserted into the via hole, thereby electrically connecting the first and the second semiconductor chips with a medium of the metal pattern. A solder ball is mounted in the ball land, and the solder ball is formed with a size that is large enough to be protruded from the second face of the second semiconductor layer.

摘要翻译： 公开了一种多芯片封装。 根据本发明，第一半导体芯片包括其中布置有焊盘的第一面和与第一面相对的第二面。 第一绝缘层涂覆在第一半导体芯片的第一面上，以露出接合焊盘。 金属图案沉积在第一绝缘层上，并且金属图案的一端连接到暴露的焊盘。 具有暴露金属图案和球面的通孔的第二绝缘层涂覆在第一半导体芯片的第一面上。 第二半导体芯片包括第一面，其中焊盘设置并与第一半导体芯片的第一面相对，第二面与第二半导体芯片的第一面相对。 第二半导体芯片与第一半导体芯片的第一面相隔一定距离。 第三绝缘层涂覆在第二半导体芯片的第一面上，以露出第二半导体芯片的焊盘。 在第二半导体芯片的接合焊盘处形成导电凸块。 将导电凸块插入到通孔中，从而将第一和第二半导体芯片与金属图案的介质电连接。 焊球安装在球场中，焊球形成的尺寸足够大以从第二半导体层的第二面突出。

公开(公告)号：US06380615B1

公开(公告)日：2002-04-30

申请号：US09604091

申请日：2000-06-27

申请人： Sang Wook Park ,  Jae Myun Kim

发明人： Sang Wook Park ,  Jae Myun Kim

IPC分类号： H01L2302

CPC分类号： H01L23/3114 ,  H01L21/563 ,  H01L23/13 ,  H01L24/27 ,  H01L24/45 ,  H01L24/48 ,  H01L24/743 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2924/00012

摘要： Disclosed are a chip size stack package, a memory module having the same and a method for fabricating the memory module. In the chip size stack package, two semiconductor chips are arranged in a manner such that their surfaces on which bonding pads are formed, are opposed to each other at a predetermined interval. Insulating layers are applied to the surfaces of the semiconductor chips on which surfaces the bonding pads are formed, in a manner such that the bonding pads are exposed. Metal traces are respectively deposited on the insulating layers and connected to the bonding pads. Solder balls electrically connect the metal traces with each other. One ends of metal wires are bonded to a side of one of the metal traces. Both sides of the semiconductor chips and a space between them are molded by an encapsulate, in a manner such that the other ends of the metal wires are exposed.

摘要翻译： 公开了一种芯片尺寸的堆叠封装，具有该封装的存储器模块和用于制造存储器模块的方法。 在芯片尺寸堆叠封装中，以这样的方式布置两个半导体芯片，使得它们在其上形成焊盘的表面以预定间隔彼此相对。 绝缘层以这样的方式施加到其上形成有接合焊盘的表面的半导体芯片的表面上，使得焊盘被暴露。 金属迹线分别沉积在绝缘层上并连接到焊盘。 焊球将金属轨迹彼此电连接。 金属线的一端结合在一个金属迹线的一侧。 半导体芯片的两侧和它们之间的空间通过密封件模制，使得金属线的另一端露出。

公开(公告)号：US08242582B2

公开(公告)日：2012-08-14

申请号：US12647657

申请日：2009-12-28

申请人： Bok Gyu Min ,  Jae Myun Kim ,  Da Un Nah

发明人： Bok Gyu Min ,  Jae Myun Kim ,  Da Un Nah

IPC分类号： H01L23/00

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package.

摘要翻译： 半导体封装包括具有拐角形状并具有电路部分的半导体芯片。 半导体芯片具有形成在包括一个或多个拐角的第一角组中的一个或多个倒角部分。 数据接合焊盘设置在半导体芯片上并与电路部分电连接。 芯片选择焊盘被布置成与包括未形成有倒角部分的角部中的至少一个的第二角部组相邻。 芯片选择板电连接到电路部分。 可以堆叠多个半导体封装，使得当另一个半导体封装由于另一个半导体封装的倒角部分堆叠而使半导体封装中的一个的芯片选择焊盘露出。