STRUCTURE AND METHOD TO REDUCE SHORTING AND PROCESS DEGRADATION IN STT-MRAM DEVICES

    公开(公告)号:US20180190900A1

    公开(公告)日:2018-07-05

    申请号:US15906154

    申请日:2018-02-27

    IPC分类号: H01L43/08 H01L43/12

    CPC分类号: H01L43/08 H01L43/02 H01L43/12

    摘要: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.