公开(公告)号：US20100317184A1

公开(公告)日：2010-12-16

申请号：US12782859

申请日：2010-05-19

Applicant: Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

Inventor： Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

IPC: H01L21/28

CPC classification number: H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

Abstract: A method for reducing interfacial layer (IL) thickness for high-k dielectrics and metal gate stack is provided. In one embodiment, the method includes forming an interfacial layer on a semiconductor substrate, etching back the interfacial layer, depositing a high-k dielectric material over the interfacial layer, and forming a metal gate over the high-k dielectric material. The IL can be chemical oxide, ozonated oxide, thermal oxide, or formed by ultraviolet ozone (UVO) oxidation process from chemical oxide, etc. The etching back of IL can be performed by a Diluted HF (DHF) process, a vapor HF process, or any other suitable process. The method can further include performing UV curing or low thermal budget annealing on the interfacial layer before depositing the high-k dielectric material.

Abstract translation: 提供了一种用于降低高k电介质和金属栅极叠层的界面层（IL）厚度的方法。 在一个实施例中，该方法包括在半导体衬底上形成界面层，蚀刻回界面层，在界面层上沉积高k电介质材料，以及在高k电介质材料上形成金属栅极。 IL可以是化学氧化物，臭氧化氧化物，热氧化物，或者由化学氧化物等的紫外线臭氧（UVO）氧化过程形成.II的回蚀可以通过稀释HF（DHF）工艺，蒸汽HF工艺 ，或任何其他合适的过程。 该方法还可以包括在沉积高k介电材料之前在界面层上进行UV固化或低热预算退火。

公开(公告)号：US20110024804A1

公开(公告)日：2011-02-03

申请号：US12831842

申请日：2010-07-07

Applicant: Chih-Hao CHANG ,  Jeff J. XU ,  Chien-Hsun WANG ,  Chih Chieh YEH ,  Chih-Hsiang CHANG

Inventor： Chih-Hao CHANG ,  Jeff J. XU ,  Chien-Hsun WANG ,  Chih Chieh YEH ,  Chih-Hsiang CHANG

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/785 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/18 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.

Abstract translation: 提供了具有高Ge浓度的SiGe应激源的制造方法。 该方法包括：提供具有源极区域，漏极区域和沟道之间的半导体衬底; 在源极区域和/或漏极区域上沉积第一SiGe膜层; 进行低温热氧化，例如高水蒸气压湿氧化，以在第一SiGe层的顶部形成氧化物层，并在第一SiGe膜的底部形成具有高Ge百分比的第二SiGe膜层 Ge层扩散到半导体衬底中; 执行热扩散以从第二SiGe膜层形成SiGe应力源，其中SiGe应力源在通道上提供单轴压缩应变; 并除去氧化物层。 在进行氧化之前，可以在第一SiGe膜层上沉积Si覆盖层。

公开(公告)号：US20120322253A1

公开(公告)日：2012-12-20

申请号：US13595599

申请日：2012-08-27

Applicant: Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

Inventor： Liang-Gi YAO ,  Chun-Hu CHENG ,  Chen-Yi LEE ,  Jeff J. XU ,  Clement Hsingjen WANN

IPC: H01L21/283 ,  H01L21/311

CPC classification number: H01L29/513 ,  H01L21/02172 ,  H01L21/022 ,  H01L21/28158 ,  H01L21/28211 ,  H01L21/283 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/78

Abstract: This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

Abstract translation: 该描述涉及包括在半导体衬底上形成界面层的方法。 该方法还包括蚀刻回界面层。 该方法还包括在界面层上进行紫外线（UV）固化过程。 UV固化方法包括将每分钟10标准立方厘米（sccm）的气体流速提供到5标准升/分钟（slm），其中气体包括惰性气体，并且在小于或等于的温度下加热界面层 至700℃。该方法还包括在界面层上沉积高k电介质材料。

公开(公告)号：US20100314687A1

公开(公告)日：2010-12-16

申请号：US12784073

申请日：2010-05-20

Applicant: Jeff J. XU

Inventor： Jeff J. XU

IPC: H01L27/092 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/49 ,  H01L21/28088 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/78 ,  H01L29/7833 ,  H01L2224/16225

Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.

Abstract translation: 提供了用于形成金属栅极晶体管的最后一种方法。 该方法包括在基底上形成电介质材料内的开口。 栅极电介质结构形成在开口内和衬底上。 工作功能金属层形成在开口内和栅介质结构之上。 在功函数金属层上形成硅化物结构。

公开(公告)号：US20110062526A1

公开(公告)日：2011-03-17

申请号：US12761918

申请日：2010-04-16

Applicant: Jeff J. XU ,  Cheng-Tung LIN ,  Hsiang-Yi WANG ,  Wen-Chin LEE ,  Betty HSIEH

Inventor： Jeff J. XU ,  Cheng-Tung LIN ,  Hsiang-Yi WANG ,  Wen-Chin LEE ,  Betty HSIEH

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823835 ,  H01L21/823842

Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.

Abstract translation: 提供了用于形成金属栅极晶体管的最后一种方法。 该方法包括在基底上形成电介质材料内的开口。 栅极电介质结构形成在开口内和衬底上。 工作功能金属层形成在开口内和栅介质结构之上。 在功函数金属层上形成硅化物结构。

公开(公告)号：US20100072553A1

公开(公告)日：2010-03-25

申请号：US12236115

申请日：2008-09-23

Applicant: Jeff J. XU ,  Clement H. Wann ,  Chih Chieh Yeh ,  Chih-Sheng Chang

Inventor： Jeff J. XU ,  Clement H. Wann ,  Chih Chieh Yeh ,  Chih-Sheng Chang

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.

Abstract translation: CMOS FinFET半导体器件提供了一种NMOS FinFET器件，其包括半导体鳍片上的压应力金属栅极层和包括半导体鳍片上的拉应力金属栅极层的PMOS FinFET器件。 其形成方法包括选择性退火工艺，其选择性地将形成在PMOS器件上的压电金属栅极膜转换为拉伸应力金属栅极膜。

公开(公告)号：US20120100681A1

公开(公告)日：2012-04-26

申请号：US12981610

申请日：2010-12-30

Applicant: Ziwei FANG ,  Jeff J. XU ,  Ming-Jie HUANG ,  Yimin HUANG ,  Zhiqiang WU ,  Min CAO

Inventor： Ziwei FANG ,  Jeff J. XU ,  Ming-Jie HUANG ,  Yimin HUANG ,  Zhiqiang WU ,  Min CAO

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes.

Abstract translation: 用于制造集成电路器件的集成电路器件和方法通过在第一掺杂区域中形成第二掺杂区域并且去除第一和第二掺杂区域，从而提供对用于形成集成电路器件的源极和漏极特征的沟槽形状的改进的控制 第二掺杂区域通过第一和第二湿蚀刻工艺。

公开(公告)号：US20120015503A1

公开(公告)日：2012-01-19

申请号：US13242090

申请日：2011-09-23

Applicant: Liang-Gi YAO ,  Chia-Cheng CHEN ,  Ta-Ming KUAN ,  Jeff J. XU ,  Clement Hsingjen WANN

Inventor： Liang-Gi YAO ,  Chia-Cheng CHEN ,  Ta-Ming KUAN ,  Jeff J. XU ,  Clement Hsingjen WANN

IPC: H01L21/20 ,  B08B5/00 ,  H01L21/336

CPC classification number: H01L21/02661 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823418 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.

Abstract translation: 形成半导体器件的方法包括化学清洗衬底的表面以在表面上形成化学氧化物材料。 化学氧化物材料的至少一部分以约2纳米/分钟（nm / min）或更小的去除速率除去。 此后，在衬底的表面上形成栅极电介质层。

公开(公告)号：US20110272739A1

公开(公告)日：2011-11-10

申请号：US12775006

申请日：2010-05-06

Applicant: Tsung-Lin LEE ,  Chih-Hao CHANG ,  Chih-Hsin KO ,  Feng YUAN ,  Jeff J. XU

Inventor： Tsung-Lin LEE ,  Chih-Hao CHANG ,  Chih-Hsin KO ,  Feng YUAN ,  Jeff J. XU

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract translation: 一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。 该凹腔具有下部和上部。 下部具有第一应变层和第一介电膜。 第一应变层设置在隔离结构和第一介电膜之间。 第一电介质膜的厚度小于第一应变层的厚度。 上部具有覆盖在第一应变层和第一介电膜上的第二应变层。