公开(公告)号：US20210057318A1

公开(公告)日：2021-02-25

申请号：US16912595

申请日：2020-06-25

申请人： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh

发明人： Jiun Hann Sir ,  Poh Boon Khoo ,  Eng Huat Goh

IPC分类号： H01L23/498 ,  H01L21/48 ,  H05K3/34

摘要： Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.

公开(公告)号：US20210098352A1

公开(公告)日：2021-04-01

申请号：US16912653

申请日：2020-06-25

申请人： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

发明人： Jiun Hann Sir ,  Eng Huat Goh ,  Poh Boon Khoo

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/552

摘要： A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

公开(公告)号：US20190035761A1

公开(公告)日：2019-01-31

申请号：US16049790

申请日：2018-07-30

申请人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

发明人： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/56

摘要： Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a second die disposed on a first die, a first plurality of interconnect structures disposed on a top surface of the first die, and a second plurality of interconnect structures disposed on a top surface of the second die. Top surfaces of the first plurality of interconnect structures are coplanar with top surfaces of the plurality of the second interconnect structures. At least one of the interconnect structures of the first or the second plurality of interconnect structures comprises a sigmoid shape.

公开(公告)号：US07217651B2

公开(公告)日：2007-05-15

申请号：US10902446

申请日：2004-07-28

申请人： Jiun Hann Sir ,  Eng Huat Goh

发明人： Jiun Hann Sir ,  Eng Huat Goh

IPC分类号： H01L21/4763

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/423 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2203/0733 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments include interconnect of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a trench and via in the dielectric layer, the via extending to the contact surface. An interlock material is in the via with an interlock opening extending through the interlock material and into the interconnect. A layer of electroless material is on the base of the trench and the surfaces of the via, interlock material, and interlock opening. An subsequent interconnect is formed on the electroless material, in the trench, via, and interlock openings. The structure can be repeated to form a stack or column of interconnects that resist delamination.

公开(公告)号：US07795736B2

公开(公告)日：2010-09-14

申请号：US11715624

申请日：2007-03-08

申请人： Jiun Hann Sir ,  Eng Huat Goh

发明人： Jiun Hann Sir ,  Eng Huat Goh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/423 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/09845 ,  H05K2203/0733 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments include interconnect of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a trench and via in the dielectric layer, the via extending to the contact surface. An interlock material is in the via with an interlock opening extending through the interlock material and into the interconnect. A layer of electroless material is on the base of the trench and the surfaces of the via, interlock material, and interlock opening. An subsequent interconnect is formed on the electroless material, in the trench, via, and interlock openings. The structure can be repeated to form a stack or column of interconnects that resist delamination.

摘要翻译： 实施例包括导电材料与接触表面的互连以及覆盖接触表面的电介质层，其中沟槽和电介质层中的通孔延伸到接触表面。 互锁材料在通孔中，具有延伸穿过互锁材料并进入互连件的互锁开口。 无电解材料层位于沟槽的底部和通孔，互锁材料和互锁开口的表面上。 在无电解材料，沟槽，通孔和互锁开口中形成随后的互连。 可以重复该结构以形成抵抗分层的互连的堆叠或列。

公开(公告)号：US20110147923A1

公开(公告)日：2011-06-23

申请号：US12643074

申请日：2009-12-21

申请人： Jiun Hann Sir

发明人： Jiun Hann Sir

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H05K3/3436 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0097 ,  H05K3/3484 ,  H05K3/4007 ,  H05K2201/0367 ,  Y02P70/613

摘要： An electronic apparatus may include a first component solder bonded to a second component. The first component may be, for example, an integrated circuit. The first component may have an array of metallic protrusions. Those protrusions may be coupled to circuit elements within said first component. The second component may include a plurality of solder portions coupled to the second component and engaged by the protrusions on the first component in a soldered connection.

摘要翻译： 电子设备可以包括结合到第二部件的第一部件焊料。 第一组件可以是例如集成电路。 第一组件可以具有金属突起的阵列。 那些突起可以耦合到所述第一部件内的电路元件。 第二部件可以包括多个焊接部分，其耦合到第二部件并且由焊接连接中的第一部件上的突起接合。

公开(公告)号：US07678616B2

公开(公告)日：2010-03-16

申请号：US12143038

申请日：2008-06-20

申请人： Jiun Hann Sir ,  Chee Koang Chen

发明人： Jiun Hann Sir ,  Chee Koang Chen

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/36 ,  H01L21/563 ,  H01L23/04 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus, method, and system for providing thermal management for an integrated circuit includes a first metallic layer directly placed on a back surface of the integrated circuit. An integrated heat spreader with a substantially cap-like shape is placed over the integrated circuit, with an aperture of a ceiling wall of the integrated heat spreader exposing a back surface of the integrated circuit at least in part. The first metallic layer is directly placed on top of an exterior surface of the ceiling wall of the integrated heat spreader as well as the back surface of the integrated circuit.

摘要翻译： 用于为集成电路提供热管理的装置，方法和系统包括直接放置在集成电路的后表面上的第一金属层。 具有基本上帽状形状的集成散热器放置在集成电路上，集成散热器的顶壁的孔至少部分地暴露集成电路的后表面。 第一金属层直接放置在集成散热器的顶壁的外表面的顶部以及集成电路的背面。

公开(公告)号：US07365007B2

公开(公告)日：2008-04-29

申请号：US10882468

申请日：2004-06-30

申请人： Jiun Hann Sir

发明人： Jiun Hann Sir

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/15311 ,  H05K3/424 ,  H05K2201/0329 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0796 ,  H01L2924/00014

摘要： Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are layered with a manganese oxide (MnO2) layer which is layered over with a conductive polymer material. An interconnect material is formed in the via and in a trench above the perimeter of the via such that the interconnect material is on the conductive polymer material and contacts the contact surface. An additional dielectric layer may be formed over the interconnect material and an additional via may be formed therethrough so that an additional structure having a MnO2 layer, conductive polymer material, and interconnect material can be formed in the additional via and to the interconnect material.

摘要翻译： 实施例包括具有接触表面的导电材料的互连或迹线，以及覆盖接触表面的电介质层与形成在电介质层和接触表面上的通孔。 通孔侧壁和周边用与导电聚合物材料层叠的氧化锰（MnO 2 N 2）层层叠。 互连材料形成在通孔的上部和通孔周边的沟槽中，使得互连材料在导电聚合物材料上并与接触表面接触。 可以在互连材料上形成另外的介电层，并且可以通过其形成另外的通孔，使得可以在另外的附加结构中形成具有MnO 2层，导电聚合物材料和互连材料的附加结构 通孔和互连材料。

公开(公告)号：US06946737B2

公开(公告)日：2005-09-20

申请号：US10917140

申请日：2004-08-11

申请人： Jiun Hann Sir ,  Kian Sin Sim

发明人： Jiun Hann Sir ,  Kian Sin Sim

IPC分类号： H01L23/498 ,  H05K3/00 ,  H05K3/42 ,  H01L23/48

CPC分类号： H05K3/0038 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/421 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2201/2072 ,  H05K2203/108 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

摘要： The invention provides a via with improved resistance to failures due to delamination voids. In one embodiment, the via may extend from above to below a bottom conductor and include an anchor section. The anchor section may mechanically interlock the via with the bottom conductor to prevent the via from being detached from the bottom conductor.

公开(公告)号：US07745912B2

公开(公告)日：2010-06-29

申请号：US11089995

申请日：2005-03-25

申请人： Jiun Hann Sir

发明人： Jiun Hann Sir

IPC分类号： H01L23/495 ,  H01L29/40

CPC分类号： H05K3/3436 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/42 ,  H05K2201/0133 ,  H05K2201/10378 ,  H05K2203/0191 ,  Y02P70/613

摘要： An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A compliance layer is physically associated with the stiffening layer, with the compliance layer adapted to absorb stress caused by mismatched thermal properties between two materials. A thru hole passes through both the stiffening layer and the compliance layer, with the thru hole being adapted to receive a solder joint. The stress absorption layer contacts both a semiconductor package and a substrate. The solder joint disposed in the thru hole connects the semiconductor package to the substrate.

摘要翻译： 用于为集成电路提供应力吸收层的装置，方法和系统包括适于限制弯曲的加强层。 柔性层与加强层物理相关，柔性层适于吸收由两种材料之间的不匹配的热性质引起的应力。 通孔穿过加强层和柔性层，通孔适于接纳焊接接头。 应力吸收层与半导体封装和衬底接触。 布置在通孔中的焊点将半导体封装连接到基板。