公开(公告)号：US08088648B2

公开(公告)日：2012-01-03

申请号：US12840656

申请日：2010-07-21

Applicant: Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L21/50 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20080157332A1

公开(公告)日：2008-07-03

申请号：US12000384

申请日：2007-12-12

Applicant: Cha-Jea Jo ,  Seok-Ho Kim ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Seok-Ho Kim ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L23/538 ,  H01L21/58

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/48463 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107

Abstract: A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package. A method of manufacturing a stacked semiconductor package may include: forming semiconductor packages; stacking the semiconductor packages on a substrate; forming a mask pattern on the semiconductor packages and the substrate to expose the edges of the semiconductor packages; performing an electroless plating process on the edges of the semiconductor packages to form a seed layer; and performing an electroplating process on the seed layer to form an interconnection member for electrically connecting the conductive lines to each other.

Abstract translation: 层叠的半导体封装可以包括：衬底; 堆叠在基板上的半导体封装; 形成在所述半导体封装的边缘上的互连构件; 以及形成在所述互连构件上的导电加强构件。 每个半导体封装可以包括导线。 互连构件可将半导体封装的导线电连接至至少一个其它半导体封装的导线。 层叠半导体封装的制造方法可以包括：形成半导体封装; 将半导体封装堆叠在衬底上; 在所述半导体封装和所述衬底上形成掩模图案以暴露所述半导体封装的边缘; 在半导体封装的边缘上进行化学镀处理以形成种子层; 以及在种子层上进行电镀处理以形成用于将导线彼此电连接的互连构件。

公开(公告)号：US20100285635A1

公开(公告)日：2010-11-11

申请号：US12840656

申请日：2010-07-21

Applicant: Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20080157287A1

公开(公告)日：2008-07-03

申请号：US12003798

申请日：2008-01-02

Applicant: Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

Inventor： Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05181 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.

Abstract translation: 提供半导体器件及其形成方法。 所述方法可以包括在初步半导体衬底中形成孔，在初步半导体衬底的孔中形成绝缘层，在绝缘层和初级半导体衬底上形成电镀导电层，形成与电镀导电性接触的晶种金属层 层，并且生长种子金属层以形成穿硅通孔（TSV）。 TSV可以通过电镀工艺形成，使得种子金属层从孔的下部生长到孔的上部。

公开(公告)号：US08178969B2

公开(公告)日：2012-05-15

申请号：US12401699

申请日：2009-03-11

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，与半导体结构电连接以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US20090230549A1

公开(公告)日：2009-09-17

申请号：US12401699

申请日：2009-03-11

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，与半导体结构电连接以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US07626260B2

公开(公告)日：2009-12-01

申请号：US11751464

申请日：2007-05-21

Applicant: Hyun-Soo Chung ,  Cha-Jea Jo ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Cha-Jea Jo ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L23/34

CPC classification number: H01L23/473 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.

Abstract translation: 提供了在其底面上具有冷却路径的半导体器件。 具有冷却路径的叠层型半导体器件包括：堆叠型半导体芯片，包括第一半导体芯片和第二半导体芯片。 第一半导体芯片包括其中形成有电路单元的第一表面和形成有第一冷却路径的第二表面，并且第二半导体芯片包括其中形成电路单元的第一表面和第二表面，其中第二表面 形成第二冷却路径。 第一半导体芯片的第二表面和第二半导体芯片的第二表面彼此接合，并且使用第一和第二冷却路径在堆叠型半导体芯片的中间形成第三冷却路径。 堆叠型半导体器件的翘曲被抑制，并且易于散热。

公开(公告)号：US08723315B2

公开(公告)日：2014-05-13

申请号：US13470572

申请日：2012-05-14

Applicant: Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

Inventor： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US07638365B2

公开(公告)日：2009-12-29

申请号：US11623279

申请日：2007-01-15

Applicant: Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

Inventor： Se-Young Jeong ,  Nam-Seog Kim ,  Cha-Jea Jo ,  Jong-Ho Lee ,  Myeong-Soon Park

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L27/146 ,  H01L27/148 ,  H01L23/02

CPC classification number: H01L23/3114 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2225/06524 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

Abstract translation: 提供一种堆叠式芯片封装及其形成方法。 间隔件形成在上芯片的一侧。 在间隔件上形成导线以电连接上芯片和下芯片。 堆叠式芯片封装的可靠性得到改善，因为引线接合不用于电连接上下芯片。 此外，堆叠的芯片封装的整体尺寸可以减小，因为接合线环的高度对整个堆叠的芯片封装高度没有贡献。