公开(公告)号：US20080157287A1

公开(公告)日：2008-07-03

申请号：US12003798

申请日：2008-01-02

Applicant: Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

Inventor： Ju-Il Choi ,  Cha-Jea Jo ,  Seok-Ho Kim ,  Chang-Woo Shin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05181 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: A semiconductor device and methods of forming the same are provided. The methods may include forming a hole in a preliminary semiconductor substrate, forming an insulating layer in the hole of the preliminary semiconductor substrate, forming a plating conductive layer on the insulating layer and the preliminary semiconductor substrate, forming a seed metal layer contacting the plating conductive layer at a lower portion of the hole and growing the seed metal layer to form a through-silicon via (TSV). The TSV may be formed through an electroplating process such that the seed metal layer grows from the lower portion of the hole to an upper portion of the hole.

Abstract translation: 提供半导体器件及其形成方法。 所述方法可以包括在初步半导体衬底中形成孔，在初步半导体衬底的孔中形成绝缘层，在绝缘层和初级半导体衬底上形成电镀导电层，形成与电镀导电性接触的晶种金属层 层，并且生长种子金属层以形成穿硅通孔（TSV）。 TSV可以通过电镀工艺形成，使得种子金属层从孔的下部生长到孔的上部。

公开(公告)号：US08088648B2

公开(公告)日：2012-01-03

申请号：US12840656

申请日：2010-07-21

Applicant: Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L21/50 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20080157332A1

公开(公告)日：2008-07-03

申请号：US12000384

申请日：2007-12-12

Applicant: Cha-Jea Jo ,  Seok-Ho Kim ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Seok-Ho Kim ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L23/538 ,  H01L21/58

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/48463 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107

Abstract: A stacked semiconductor package may include: a substrate; semiconductor packages stacked on the substrate; an interconnection member formed on edges of the semiconductor packages; and a conductive reinforcement member formed on the interconnection member. Each of the semiconductor packages may include a conductive line. The interconnection member may electrically connect the conductive line of the semiconductor packages to the conductive line of at least one other semiconductor package. A method of manufacturing a stacked semiconductor package may include: forming semiconductor packages; stacking the semiconductor packages on a substrate; forming a mask pattern on the semiconductor packages and the substrate to expose the edges of the semiconductor packages; performing an electroless plating process on the edges of the semiconductor packages to form a seed layer; and performing an electroplating process on the seed layer to form an interconnection member for electrically connecting the conductive lines to each other.

Abstract translation: 层叠的半导体封装可以包括：衬底; 堆叠在基板上的半导体封装; 形成在所述半导体封装的边缘上的互连构件; 以及形成在所述互连构件上的导电加强构件。 每个半导体封装可以包括导线。 互连构件可将半导体封装的导线电连接至至少一个其它半导体封装的导线。 层叠半导体封装的制造方法可以包括：形成半导体封装; 将半导体封装堆叠在衬底上; 在所述半导体封装和所述衬底上形成掩模图案以暴露所述半导体封装的边缘; 在半导体封装的边缘上进行化学镀处理以形成种子层; 以及在种子层上进行电镀处理以形成用于将导线彼此电连接的互连构件。

公开(公告)号：US20100285635A1

公开(公告)日：2010-11-11

申请号：US12840656

申请日：2010-07-21

Applicant: Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20120292195A1

公开(公告)日：2012-11-22

申请号：US13438020

申请日：2012-04-03

Applicant: Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

Inventor： Ui Hyoung LEE ,  Ju-Il Choi ,  Jae-Hyun Phee ,  Dong Hyeon Jang ,  Jeong-Woo Park

IPC: C25B15/00 ,  C25B9/00

CPC classification number: C25D17/001 ,  C25D5/02 ,  C25D5/08 ,  C25D7/123 ,  C25D17/008 ,  H01L21/2885

Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.

Abstract translation: 一种用于电镀半导体器件的设备包括一个容纳电镀溶液的电镀液和一个在电镀槽中的一个电极板，该电极板包括多个孔，该多个孔被配置成将电镀液通过桨向衬底通过，电镀液流动加强 所述部分被配置为选择性地将所述电镀溶液的流动加强到所述基板的预定区域，所述基板的所述预定区域是需要相对增加所述电镀液的金属离子供应的区域。

公开(公告)号：US07544538B2

公开(公告)日：2009-06-09

申请号：US11775120

申请日：2007-07-09

Applicant: Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract translation: 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20160086874A1

公开(公告)日：2016-03-24

申请号：US14858572

申请日：2015-09-18

Applicant: Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01047

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

Abstract translation: 半导体器件可以包括具有表面的衬底。 通孔结构可以延伸穿过衬底朝向衬底的表面，其中通孔结构包括上表面。 衬垫结构可以在衬底的表面上，其中衬垫结构可以包括具有至少一个突起的下表面，其被配置为朝向通孔结构的上表面突出。

公开(公告)号：US08482129B2

公开(公告)日：2013-07-09

申请号：US13027594

申请日：2011-02-15

Applicant: In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

Inventor： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。

公开(公告)号：US20110097891A1

公开(公告)日：2011-04-28

申请号：US12906578

申请日：2010-10-18

Applicant: Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

Inventor： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

Abstract translation: 制造半导体器件的方法包括制备具有与第一表面相对的第一表面和第二表面的衬底。 在第二表面上形成第一绝缘层。 牺牲层形成在第一绝缘层上。 形成开口以穿透基底并从第一表面延伸到牺牲层的一部分。 第二绝缘层形成在开口的内壁上。 形成塞子以填充开口。 去除牺牲层以通过第二表面暴露插塞的下部。

公开(公告)号：US09082680B2

公开(公告)日：2015-07-14

申请号：US13535766

申请日：2012-06-28

Applicant: Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

Inventor： Ju-Il Choi ,  Jeong-Gi Jin ,  Ui-Hyoung Lee ,  Hyung-Seok Kim ,  Jeong-Woo Park

IPC: H05K1/16 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34 ,  B23K1/00 ,  H01L25/065 ,  H01L25/10 ,  H05K3/40 ,  H01L23/31

CPC classification number: H01L24/16 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2224/13686 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/181 ,  H05K3/3442 ,  H05K3/3489 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/053 ,  H01L2924/00012

Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.

Abstract translation: 本发明构思提供了在形成包括一个或多个防腐膜的焊接结构和焊点结构期间，抑制在金属凸块上形成一种或多种氧化物的方法。 在一些实施例中，焊点结构包括具有设置在其表面上的防腐膜的金属凸块。