公开(公告)号：US06781222B2

公开(公告)日：2004-08-24

申请号：US09932053

申请日：2001-08-18

Applicant: Chi Chuan Wu ,  Chian Ping Huang ,  Jui-Yu Chuang ,  Ho-Yi Tsai ,  Yude Chu

Inventor： Chi Chuan Wu ,  Chian Ping Huang ,  Jui-Yu Chuang ,  Ho-Yi Tsai ,  Yude Chu

IPC: H01L2306

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/642 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package and its fabricating method are proposed, in which a plurality of passive devices are integrated under a semiconductor chip, so as to increase the layout number of the passive devices in the semiconductor package and enhance the flexibility of substrate routability, as well as reduce an occupied area of a substrate for miniaturize the semiconductor package in profile. Moreover, as the integrated passive devices are further encapsulated by using an insulative material prior to a molding process, the dislocation of the passive devices caused by a high temperature and mold flow of a molding resin can be prevented from occurrence during molding. Furthermore, the encapsulated passive devices are prevented from contacting bonding wires, allowing the occurrence of short circuit to be avoided and quality of the packaged product to be assured.

Abstract translation: 提出了一种半导体封装及其制造方法，其中多个无源器件集成在半导体芯片之下，以便增加半导体封装中的无源器件的布局数量并提高衬底可路由性的灵活性，以及 减少基板的占用面积，以使半导体封装的形状小型化。 此外，由于通过在模制工艺之前使用绝缘材料进一步封装集成的无源器件，因此可以防止在模制期间由模制树脂的高温和模具流引起的无源器件的位错。 此外，防止封装的无源器件接触接合线，从而避免短路的发生，并确保封装产品的质量。

公开(公告)号：USD529031S1

公开(公告)日：2006-09-26

申请号：US29210201

申请日：2004-07-27

Applicant: Chih-Ming Huang ,  Chien-Ping Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan ,  Cheng-Hsu Hsiao

Designer： Chih-Ming Huang ,  Chien-Ping Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan ,  Cheng-Hsu Hsiao

公开(公告)号：US06472743B2

公开(公告)日：2002-10-29

申请号：US09973151

申请日：2001-10-09

Applicant: Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chih Chan ,  Ming-Chih Hsieh

Inventor： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chih Chan ,  Ming-Chih Hsieh

IPC: H01L2334

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package with a heat dissipating structure is proposed, in which the heat dissipating structure is precisely positioned on a substrate, in a manner that a plurality of solder balls self-align with ball pads formed on the substrate, and support a heat sink to be positioned above a semiconductor chip mounted on the substrate. This therefore makes the heat sink closely abut a molding cavity of an encapsulating mold in a molding process, and prevents resin flash from occurring on the heat sink, so that a surface of the heat sink can be directly exposed to the atmosphere for improving heat dissipating efficiency. Moreover, the solder balls characterized in softness deform in response to a pressure generated by the encapsulating mold during molding. Therefore, the substrate can be protected from being damaged by the pressure, and thus quality of the semiconductor package can be assured.

Abstract translation: 提出了一种具有散热结构的半导体封装，其中散热结构精确地定位在基板上，使得多个焊球与衬底上形成的球垫自对准，并且支撑散热器 位于安装在基板上的半导体芯片的上方。 因此，在成型工序中，散热片紧密地邻接封装模具的模腔，并且防止散热片上发生树脂闪光，使得散热片的表面可以直接暴露于大气中以改善散热 效率。 此外，柔软的焊料球响应于在模制期间由封装模具产生的压力而变形。 因此，可以防止基板受到压力的损害，从而可以确保半导体封装的质量。

公开(公告)号：US07339280B2

公开(公告)日：2008-03-04

申请号：US10319211

申请日：2002-12-13

Applicant: Jui-Yu Chuang ,  Lien-Chi Chan ,  Chih-Ming Huang

Inventor： Jui-Yu Chuang ,  Lien-Chi Chan ,  Chih-Ming Huang

IPC: H01L23/29

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame includes a die pad and a plurality of leads properly spaced apart from the die pad, each lead being composed of an inner lead portion and an outer lead portion, wherein the inner lead portion is directed toward the die pad, and the outer lead portion has a terminal. At least a chip is mounted on the die pad, and a first encapsulant is formed for encapsulating the chip, die pad and inner lead portions. An injection-molded second encapsulant is formed for encapsulating the first encapsulant and outer lead portions, but exposing the terminals of the outer lead portions. The second encapsulant made by injection molding can prevent resin flash over the exposed terminals, thereby assuring electrical-connection quality of the semiconductor package.

Abstract translation: 提供了具有引线框架作为芯片载体的半导体封装及其制造方法。 引线框架包括管芯焊盘和与管芯焊盘适当间隔开的多个引线，每个引线由内引线部分和外引线部分组成，其中内引线部分指向管芯焊盘，外引线 引线部分具有端子。 至少芯片安装在管芯焊盘上，形成第一密封剂以封装芯片，管芯焊盘和内引线部分。 形成注射成型的第二密封剂，用于封装第一密封剂和外引线部分，但暴露外引线部分的端子。 通过注射成型制成的第二密封剂可以防止树脂在暴露的端子上闪烁，从而确保半导体封装的电连接质量。

公开(公告)号：US06858931B2

公开(公告)日：2005-02-22

申请号：US10329093

申请日：2002-12-23

Applicant: Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

Inventor： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/433 ,  H01L23/10 ,  H01L23/34

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.

Abstract translation: 提出了具有塌陷结构的散热器和具有散热器的半导体器件，其中散热器由于散热器的延伸部分和主体之间形成的高度差而呈阶梯状，并且主体 具有暴露于半导体封装外部的至少一个表面。 延伸部分在模制过程中响应于模具接合的应力而产生塌陷变形，以防止半导体芯片被应力损坏。 直接连接到芯片的散热片允许由芯片产生的热量穿过延伸部分到达散热体的主体，然后可以将热量通过主体的暴露表面散发到半导体封装的外部， 从而提高散热效率。

公开(公告)号：US06483178B1

公开(公告)日：2002-11-19

申请号：US09616729

申请日：2000-07-14

Applicant: Jui-Yu Chuang

Inventor： Jui-Yu Chuang

IPC: H01L23495

CPC classification number: H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package structure is proposed, which allows the encapsulation body to be highly secured in position to the leads, making the encapsulation body hardly delaminated from the leads. The proposed semiconductor device package structure comprises a die pad; a semiconductor chip mounted on the die pad; a plurality of leads arranged around the die pad, each lead being formed with a bolting hole; a plurality of bonding wires for electrically coupling the semiconductor chip to the leads; and an encapsulation body which encapsulates the semiconductor chip and the bonding wires and includes a part filled in the bolting hole in each of the leads. The bolting hole is characterized in the forming of a constricted middle part or an inclined orientation with respect to the lead surface, which allows the encapsulation body to be highly secured in position to the leads, thereby making the encapsulation body hardly delaminated from the leads. As a result, the finished package product can be highly assured in quality and reliability.

Abstract translation: 提出了一种半导体器件封装结构，其允许封装体高度固定在引线的位置，使得封装体几乎不与引线分层。 所提出的半导体器件封装结构包括管芯焊盘; 安装在芯片焊盘上的半导体芯片; 多个引线布置在芯片焊盘周围，每个引线形成有螺栓孔; 用于将半导体芯片电耦合到引线的多个接合线; 以及封装体，其封装半导体芯片和接合线，并且包括填充在每个引线中的螺栓孔中的部分。 螺栓孔的特征在于形成收缩的中间部分或相对于引线表面的倾斜取向，这允许封装体高度固定在引线的位置，从而使封装体几乎不与引线分层。 因此，成品包装产品在质量和可靠性方面可以高度保证。

公开(公告)号：US06847104B2

公开(公告)日：2005-01-25

申请号：US10377545

申请日：2003-02-27

Applicant: Chien Ping Huang ,  Chih-Ming Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan

Inventor： Chien Ping Huang ,  Chih-Ming Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/495 ,  H01L23/02

CPC classification number: H01L23/16 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A window-type ball grid array (WBGA) semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The lead frame has a plurality of leads encompassing an opening, each lead having an upper surface and an opposing lower surface. A resin material is pre-molded on the lower surfaces of the leads, with wire-bonding portions and ball-implanting portions defined on the leads being exposed. At least a chip is mounted on the upper surfaces of the leads and covers the opening, allowing the chip to be electrically connected to the wire-bonding portions of the leads by a plurality of bonding wires via the opening. Then, an encapsulant is formed to encapsulate the chip and fill into the opening for encapsulating the bonding wires. Finally, solder balls are implanted on the ball-implanting portions of the leads to complete fabrication of the semiconductor package.

Abstract translation: 提供了一种具有引线框架作为芯片载体的窗型球栅阵列（WBGA）半导体封装及其制造方法。 引线框架具有包围开口的多个引线，每个引线具有上表面和相对的下表面。 在引线的下表面上预先模塑树脂材料，其中限定在引线上的引线接合部分和球注入部分被暴露。 至少芯片安装在引线的上表面上并覆盖开口，允许芯片通过多个接合线通过开口与引线的引线接合部分电连接。 然后，形成密封剂以封装芯片并填充到用于封装接合线的开口中。 最后，将焊球注入到引线的球注入部分上以完成半导体封装的制造。

公开(公告)号：USD492314S1

公开(公告)日：2004-06-29

申请号：US29192300

申请日：2003-10-21

Applicant: Chih-Ming Huang ,  Chien-Ping Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan ,  Cheng-Hsu Hsiao

Designer： Chih-Ming Huang ,  Chien-Ping Huang ,  Jui-Yu Chuang ,  Lien-Chi Chan ,  Cheng-Hsu Hsiao

公开(公告)号：US06538321B2

公开(公告)日：2003-03-25

申请号：US09946999

申请日：2001-09-05

Applicant: Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

Inventor： Chien-Ping Huang ,  Chi-Chuan Wu ,  Jui-Yu Chuang ,  Lien-Chi Chan

IPC: H01L2310

CPC classification number: H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.