公开(公告)号：US08970516B2

公开(公告)日：2015-03-03

申请号：US13235158

申请日：2011-09-16

申请人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

发明人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

IPC分类号： G06F3/041 ,  G02B26/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： G02B26/001 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

摘要： This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

摘要翻译： 本公开提供了用于组合沉积在第一衬底上的器件与形成在第二衬底（例如半导体衬底或玻璃衬底）上的集成电路的系统，方法和装置。 第一基板可以是玻璃基板。 第一衬底可以包括导电通孔。 功率组合器电路可以沉积在第一衬底的第一侧上。 功率组合器电路可以包括沉积在第一衬底的至少第一侧上的无源器件。 集成电路可以包括设置在功率合成器电路上并被配置为与功率组合器电路电连接的功率放大器电路，以形成功率放大系统。 导电通孔可以包括被配置为用于传导来自功率放大系统的热的热通孔和/或配置用于功率放大系统和第一衬底的第二侧上的导体之间的电连接的互连通孔。

公开(公告)号：US20120075216A1

公开(公告)日：2012-03-29

申请号：US13235158

申请日：2011-09-16

申请人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

发明人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

IPC分类号： G06F3/041 ,  H01L21/02 ,  H03F3/04 ,  H01L27/06

CPC分类号： G02B26/001 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

摘要： This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

摘要翻译： 本公开提供了用于组合沉积在第一衬底上的器件与形成在第二衬底（例如半导体衬底或玻璃衬底）上的集成电路的系统，方法和装置。 第一基板可以是玻璃基板。 第一衬底可以包括导电通孔。 功率组合器电路可以沉积在第一衬底的第一侧上。 功率组合器电路可以包括沉积在第一衬底的至少第一侧上的无源器件。 集成电路可以包括设置在功率合成器电路上并被配置为与功率组合器电路电连接的功率放大器电路，以形成功率放大系统。 导电通孔可以包括被配置为用于传导来自功率放大系统的热的热通孔和/或配置用于功率放大系统和第一衬底的第二侧上的导体之间的电连接的互连通孔。

公开(公告)号：US20140035935A1

公开(公告)日：2014-02-06

申请号：US13566925

申请日：2012-08-03

申请人： Ravindra V. Shenoy ,  Kwan-Yu Lai ,  Jon Bradley Lasiter ,  Jonghae Kim ,  Mario Francisco Velez ,  Chi Shun Lo ,  Donald William Kidwell ,  Philip Jason Stephanou ,  Justin Phelps Black ,  Evgeni Petrovich Gousev

发明人： Ravindra V. Shenoy ,  Kwan-Yu Lai ,  Jon Bradley Lasiter ,  Jonghae Kim ,  Mario Francisco Velez ,  Chi Shun Lo ,  Donald William Kidwell ,  Philip Jason Stephanou ,  Justin Phelps Black ,  Evgeni Petrovich Gousev

IPC分类号： H05K7/00 ,  H01F41/00 ,  G06T1/00 ,  H01L21/56 ,  H05K1/00 ,  H05K1/09 ,  H01R43/20 ,  H01L23/29

CPC分类号： H01L23/15 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  Y10T29/4902 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2924/00012

摘要： This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided.

摘要翻译： 本公开提供了可用于紧凑型三维封装（包括嵌入式晶片级封装）的玻璃通孔条的系统，方法和装置。 玻璃通孔棒可以在封装中提供高密度电连接。 在一些实施方案中，玻璃通孔棒可以包括集成的无源部件。 提供制造玻璃通孔条的方法。 在一些实施方案中，所述方法可以包括图案化和蚀刻可光图案化的玻璃基板。 还提供了采用玻璃通孔条的包装方法。

公开(公告)号：US20130293337A1

公开(公告)日：2013-11-07

申请号：US13463583

申请日：2012-05-03

申请人： Chi Shun Lo ,  Wesley Nathaniel Allen ,  Jonghae Kim ,  Je-Hsiung Jeffrey Lan ,  Ravindra V. Shenoy ,  Justin Phelps Black ,  Chengjie Zuo ,  Changhan Hobie Yun

发明人： Chi Shun Lo ,  Wesley Nathaniel Allen ,  Jonghae Kim ,  Je-Hsiung Jeffrey Lan ,  Ravindra V. Shenoy ,  Justin Phelps Black ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC分类号： H01F5/00 ,  H01F41/04

CPC分类号： H01F5/003 ,  H01F41/041 ,  Y10T29/4902

摘要： This disclosure provides systems, methods, and apparatus related to inductors. In one aspect, a planar inductor may include a substrate with a spacer in the shape of a planar spiral coil on a surface of the substrate. Disposed on the spacer may be a line of metal formed as a planar inductor in the shape of the planar spiral coil. The spacer may be between the line of metal and the surface of the substrate. The spacer may elevate the line of metal above the surface of the substrate.

摘要翻译： 本公开提供了与电感器相关的系统，方法和装置。 一方面，平面电感器可以包括在衬底的表面上具有平面螺旋线圈形状的间隔物的衬底。 设置在间隔件上的金属线可以是形成为平面螺旋线圈形状的平面电感器的金属线。 间隔物可以在金属线和基底的表面之间。 间隔物可以将衬底上的金属线提升。

公开(公告)号：US20140028543A1

公开(公告)日：2014-01-30

申请号：US13562168

申请日：2012-07-30

申请人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

发明人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC分类号： H01F5/00 ,  B05D5/12 ,  C25D5/02 ,  G06T1/00 ,  G06F3/01 ,  G06F1/16 ,  B05D3/10

CPC分类号： H01F17/0006 ,  G02B26/001 ,  H01F27/2804 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/00 ,  H01L2924/0002

摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.

摘要翻译： 本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。 一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。

公开(公告)号：US09001031B2

公开(公告)日：2015-04-07

申请号：US13562168

申请日：2012-07-30

申请人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

发明人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC分类号： G09G5/00 ,  H01B13/00 ,  H01F17/00 ,  H01F27/28 ,  H01L23/522 ,  H01L49/02 ,  G02B26/00

CPC分类号： H01F17/0006 ,  G02B26/001 ,  H01F27/2804 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/00 ,  H01L2924/0002

摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.

摘要翻译： 本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。 一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。

公开(公告)号：US20140035702A1

公开(公告)日：2014-02-06

申请号：US13563252

申请日：2012-07-31

申请人： Justin Phelps Black ,  Philip Jason Stephanou ,  Jonghae Kim ,  Je-Hsiung Jeffrey Lan ,  Sang-June Park ,  Changhan Hobie Yun ,  Chi Shun Lo ,  Chengjie Zuo

发明人： Justin Phelps Black ,  Philip Jason Stephanou ,  Jonghae Kim ,  Je-Hsiung Jeffrey Lan ,  Sang-June Park ,  Changhan Hobie Yun ,  Chi Shun Lo ,  Chengjie Zuo

IPC分类号： H03H9/00 ,  H03H7/01

CPC分类号： H03H7/075 ,  H03H9/465 ,  H03H2007/006

摘要： This disclosure provides implementations of filters and filter topologies, circuits, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes one or more LC resonant circuit stages. In some implementations, each LC stage includes an inductor and a capacitor. Each LC stage also has a corresponding resonant frequency. The one or more LC stages are arranged to produce an unmodified passband over a range of frequencies having a corresponding bandwidth. One or more microelectromechanical systems (MEMS) resonators are arranged with the one or more LC stages. The one or more MEMS resonators are arranged with the one or more LC stages so as to modify characteristics of the unmodified passband such that the hybrid filter produces a modified passband having a modified bandwidth and one or more other modified band characteristics.

摘要翻译： 本公开提供了滤波器和滤波器拓扑，电路，结构，设备，装置，系统和相关过程的实现。 在一个方面，器件包括一个或多个LC谐振电路级。 在一些实现中，每个LC级包括电感器和电容器。 每个LC级还具有相应的谐振频率。 一个或多个LC级布置成在具有相应带宽的频率范围上产生未修改的通带。 一个或多个微机电系统（MEMS）谐振器与一个或多个LC级布置。 一个或多个MEMS谐振器被布置成具有一个或多个LC级，以便修改未修改的通带的特性，使得混合滤波器产生具有修改的带宽和一个或多个其它修改的频带特性的修改的通带。

公开(公告)号：US09099986B2

公开(公告)日：2015-08-04

申请号：US13295970

申请日：2011-11-14

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

IPC分类号： H01L41/053 ,  H03H9/46 ,  H03H9/24 ,  H03H9/02

CPC分类号： H03H9/462 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/2426 ,  H03H2009/02503 ,  H03H2009/241

摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.

摘要翻译： 公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。 压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T） 。 厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿着Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号 到一个或多个电极。 梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。

公开(公告)号：US20130083044A1

公开(公告)日：2013-04-04

申请号：US13295970

申请日：2011-11-14

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

IPC分类号： G06F13/14 ,  H01L41/053 ,  H01L41/047

CPC分类号： H03H9/462 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/2426 ,  H03H2009/02503 ,  H03H2009/241

摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.

摘要翻译： 公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。 压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T） 。 厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿着Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号 到一个或多个电极。 梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。

公开(公告)号：US20130082799A1

公开(公告)日：2013-04-04

申请号：US13295978

申请日：2011-11-14

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim ,  Sanghoon Joo

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim ,  Sanghoon Joo

IPC分类号： H03H9/58 ,  H01L41/04

CPC分类号： H03H9/462 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/2426 ,  H03H2009/02503 ,  H03H2009/241

摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.

摘要翻译： 公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。 压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T） 。 厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号 到一个或多个电极。 梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。