公开(公告)号：US5394013A

公开(公告)日：1995-02-28

申请号：US124846

申请日：1993-09-22

申请人： Kazutoshi Oku ,  Masahiro Hirosue

发明人： Kazutoshi Oku ,  Masahiro Hirosue

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/48 ,  H01L29/54

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L24/78 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041

摘要： A bonding pad comprises a central film and a peripheral film. The peripheral film is formed around the central film, including a film formed at the same time as the central film, and being continuous with the central film. The level of the central film is made equal to or higher than the level of a protective film on the peripheral film by central film raising means. Therefore, even if the wire moves in a lateral direction when the tip of a wire is pressed against the central film, the tip of the wire does not collide with the protective film. Accordingly, it is possible to avoid the case where cracks are generated in the surface protecting film during wire bonding because of a lateral movement of the wire.

摘要翻译： 焊盘包括中心膜和外围膜。 周边膜形成在中心膜周围，包括与中心膜同时形成的膜，并与中心膜连续。 通过中央膜提起装置使中心膜的水平等于或高于周边膜上的保护膜的水平。 因此，即使当线的顶端压靠中心膜时线也沿横向方向移动，线的顶端不会与保护膜碰撞。 因此，可以避免由于导线的横向移动而引线接合期间的表面保护膜产生裂纹的情况。

公开(公告)号：US08110878B2

公开(公告)日：2012-02-07

申请号：US13179163

申请日：2011-07-08

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07982271B2

公开(公告)日：2011-07-19

申请号：US12901858

申请日：2010-10-11

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US20090179247A1

公开(公告)日：2009-07-16

申请号：US12354254

申请日：2009-01-15

申请人： Masako FUJII ,  Shigeki Obayashi ,  Naozumi Morino ,  Atsushi Hiraiwa ,  Shinichi Watarai ,  Takeshi Yoshida ,  Kazutoshi Oku ,  Masao Sugiyama ,  Yoshinori Kondo ,  Yuichi Egawa ,  Yoshiyuki Kaneko

发明人： Masako FUJII ,  Shigeki Obayashi ,  Naozumi Morino ,  Atsushi Hiraiwa ,  Shinichi Watarai ,  Takeshi Yoshida ,  Kazutoshi Oku ,  Masao Sugiyama ,  Yoshinori Kondo ,  Yuichi Egawa ,  Yoshiyuki Kaneko

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L21/823892 ,  H01L27/092

摘要： A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.

摘要翻译： 在具有三重阱结构的半导体器件中提供了可以提高制造成品率和产品可靠性的技术。 形成在浅p型阱中的n沟道型场效应晶体管和形成在浅n型阱中的p沟道型场效应晶体管并且对电路操作无贡献的逆变器电路设置在 在p型衬底中形成深n型阱; 使用第一层的布线将浅的p型阱连接到基板; 并且p沟道型场效应晶体管的栅电极和n沟道型场效应晶体管的栅电极使用最上层的布线连接到浅n型阱。

公开(公告)号：US5354702A

公开(公告)日：1994-10-11

申请号：US84092

申请日：1993-07-01

申请人： Eiichi Arima ,  Akira Nishimoto ,  Shinichi Jintate ,  Kazuo Sudo ,  Kazutoshi Oku

发明人： Eiichi Arima ,  Akira Nishimoto ,  Shinichi Jintate ,  Kazuo Sudo ,  Kazutoshi Oku

IPC分类号： H01L51/05 ,  H01L21/3205 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

CPC分类号： H01L21/32055 ,  H01L29/7883 ,  Y10S257/914

摘要： A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.

摘要翻译： 一种制造EEPROM的方法包括当用作选择栅电极的第一多晶硅层和用作第二多晶硅层的情况下，使用含有分子量大于44的有机化合物的原料气体，例如乙酸乙酯和四氢呋喃的步骤 通过CVD工艺沉积浮栅电极。 上述步骤允许电子隧穿时的电压降低。

公开(公告)号：US5252847A

公开(公告)日：1993-10-12

申请号：US241887

申请日：1988-09-08

申请人： Eiichi Arima ,  Akira Nishimoto ,  Shinichi Jintate ,  Kazuo Sudo ,  Kazutoshi Oku

发明人： Eiichi Arima ,  Akira Nishimoto ,  Shinichi Jintate ,  Kazuo Sudo ,  Kazutoshi Oku

IPC分类号： H01L51/05 ,  H01L21/3205 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L21/32055 ,  H01L29/7883 ,  Y10S257/914

摘要： A method for manufacturing an EEPROM comprises the step of using raw gas containing an organic compound having a molecular weight of more than 44, such as ethyl acetate and tetrahydrofuran when a first polysilicon layer serving as a select gate electrode and a second polysilicon layer serving as a floating gate electrode are deposited by a CVD process. The above described step allows a voltage at the time of tunneling electrons to be decreased.

摘要翻译： 一种制造EEPROM的方法包括当用作选择栅电极的第一多晶硅层和用作第二多晶硅层的情况下，使用含有分子量大于44的有机化合物的原料气体，例如乙酸乙酯和四氢呋喃的步骤 通过CVD工艺沉积浮栅电极。 上述步骤允许电子隧穿时的电压降低。

公开(公告)号：US20110024847A1

公开(公告)日：2011-02-03

申请号：US12901858

申请日：2010-10-11

申请人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： NAOZUMI MORINO ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L27/092

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07821076B2

公开(公告)日：2010-10-26

申请号：US12422278

申请日：2009-04-12

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。