公开(公告)号：US06372554B1

公开(公告)日：2002-04-16

申请号：US09390682

申请日：1999-09-07

申请人： Keizo Kawakita ,  Kazuhiko Kajigaya ,  Seiji Narui ,  Kiyoshi Nakai ,  Kazunari Suzuki ,  Hideaki Tsugane ,  Fumiyoshi Sato

发明人： Keizo Kawakita ,  Kazuhiko Kajigaya ,  Seiji Narui ,  Kiyoshi Nakai ,  Kazunari Suzuki ,  Hideaki Tsugane ,  Fumiyoshi Sato

IPC分类号： H01L2182

CPC分类号： H01L27/10894 ,  H01L23/5258 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or “synthetic” pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.

摘要翻译： 覆盖在TEG区域中形成的熔丝的多于一个的导电层的图案经过OR处理; 此外，通过转印技术将连接到所述熔丝的一个或多个测试焊盘的开口图案的组合或“合成”图案复制到涂覆在半导体晶片的表面上的感光性树脂层，从而迫使 树脂层仅驻留在划线区域的选定区域中，合成图案已转移到该区域。

公开(公告)号：US08093130B2

公开(公告)日：2012-01-10

申请号：US12022363

申请日：2008-01-30

申请人： Keizo Kawakita

发明人： Keizo Kawakita

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L27/10808 ,  H01L27/10885

摘要： This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions which are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.

摘要翻译： 该半导体器件具有MOS晶体管，其配备有形成在半导体衬底上的栅极电极，与栅电极的一侧相邻的源极区域和与栅电极另一侧相邻的漏极区域，源极的上端 区域，并且漏极区域的上端处于比半导体衬底的顶表面高的位置，并且漏极区域的上端的高度与源极区域的上端的高度不同。

公开(公告)号：US20110221034A1

公开(公告)日：2011-09-15

申请号：US12882454

申请日：2010-09-15

申请人： Keizo Kawakita

发明人： Keizo Kawakita

IPC分类号： H01L29/92

CPC分类号： H01L27/10894 ,  H01L21/7682 ,  H01L27/10855 ,  H01L27/10888

摘要： A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region.

摘要翻译： 半导体存储装置包括外围电路区域，该外围电路区域包括具有布线图案的布线层，形成在布线层的布线图案之间的非布线区域中的空腔和形成限定空腔的壁的至少一部分的绝缘膜 ，以及存储单元区域。

公开(公告)号：US06638811B2

公开(公告)日：2003-10-28

申请号：US10157977

申请日：2002-05-31

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L218242

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US06258649B1

公开(公告)日：2001-07-10

申请号：US09389231

申请日：1999-09-03

申请人： Yoshitaka Nakamura ,  Masayoshi Hirasawa ,  Isamu Asano ,  Tsuyoshi Tamaru ,  Satoru Yamada ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Takuya Fukuda

发明人： Yoshitaka Nakamura ,  Masayoshi Hirasawa ,  Isamu Asano ,  Tsuyoshi Tamaru ,  Satoru Yamada ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Takuya Fukuda

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/53223 ,  H01L27/10882 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

摘要翻译： 为了提高连接到DRAM的每个信息存储电容元件的电极的馈电互连的连接可靠性，形成用于连接在每个存储单元选择MISFET上形成的信息存储电容元件的通孔和馈电互连 在与形成用于连接在信息存储电容元件上形成的外围电路中的第二布线层的互连的通孔和形成用于连接对应于第一布线层的互连的通孔中。

公开(公告)号：US6077735A

公开(公告)日：2000-06-20

申请号：US708104

申请日：1996-08-28

申请人： Yuji Ezaki ,  Shinya Nishio ,  Fumiaki Saitoh ,  Hideo Nagasawa ,  Toshiyuki Kaeriyama ,  Songsu Cho ,  Hisao Asakura ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita

发明人： Yuji Ezaki ,  Shinya Nishio ,  Fumiaki Saitoh ,  Hideo Nagasawa ,  Toshiyuki Kaeriyama ,  Songsu Cho ,  Hisao Asakura ,  Jun Murata ,  Yoshitaka Tadaki ,  Toshihiro Sekiguchi ,  Keizo Kawakita

IPC分类号： H01L21/316 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108

CPC分类号： H01L21/76218 ,  H01L21/823493 ,  H01L21/823878

摘要： A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

摘要翻译： 制造半导体器件的方法，其能够通过去除与深孔形成相关的LOCOS氧化的残留应力来控制杂质浓度和精细图案化。 形成用于分离半导体衬底的主平面上的元件区域的选择性氧化物层，例如p型硅衬底1.在包括选择性氧化物层的表面上形成掩模（例如光致抗蚀剂47） 通过掩模中的开口引入与半导体衬底的导电类型相反的导电类型的杂质（例如磷）。 然后，通过引入杂质形成深阱（例如n型深阱50），通过高温处理退火选择性氧化物膜。

公开(公告)号：US07525829B2

公开(公告)日：2009-04-28

申请号：US11543867

申请日：2006-10-06

申请人： Keizo Kawakita ,  Yoshinori Tanaka

发明人： Keizo Kawakita ,  Yoshinori Tanaka

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2211/4013

摘要： A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second bit lines) in terminal memory mats 101A, 101C is not connected to first sense amplifiers SA1. Second sense amplifiers SA2 are arranged on the outside of the terminal memory mats, and second bit lines are connected according to a folded bit line system to the second sense amplifiers SA2. Two memory cells provided at the points where a word line WL intersects with a pair of bit lines BL, /BL connected to the second sense amplifiers SA2 constitute a twin cell unit TWC for storing a single bit of data in complementary fashion.

摘要翻译： 一种半导体存储装置，其能够有效地利用虚拟单元并提高存储单元的密度。 端子存储垫101A，101C中的每行第二行位线（第二位线）未连接到第一读出放大器SA1。 第二读出放大器SA2布置在终端存储器垫的外侧，并且第二位线根据折叠的位线系统连接到第二读出放大器SA2。 在字线WL与连接到第二读出放大器SA2的一对位线BL，/ BL相交的点处提供的两个存储单元构成用于以互补方式存储单位数据的双胞单元TWC。

公开(公告)号：US20080179650A1

公开(公告)日：2008-07-31

申请号：US12022363

申请日：2008-01-30

申请人： Keizo Kawakita

发明人： Keizo Kawakita

IPC分类号： H01L29/94 ,  H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823425 ,  H01L27/10808 ,  H01L27/10885

摘要： This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.

摘要翻译： 该半导体器件具有MOS晶体管，其配备有形成在半导体衬底上的栅极电极，与栅电极的一侧相邻的源极区域和与栅电极另一侧相邻的漏极区域，源极的上端 区域，漏极区域的上端位于比半导体衬底的顶表面高的位置，漏极区域的上端的高度与源极区域的上端的高度不同。

公开(公告)号：US20080014736A1

公开(公告)日：2008-01-17

申请号：US11822338

申请日：2007-07-05

申请人： Keizo Kawakita

发明人： Keizo Kawakita

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L27/10855 ,  H01L27/10888

摘要： A semiconductor device including a polysilicon plug with a reduced contact resistance and a manufacturing process therefor. The process includes the steps of forming a hole in an insulating layer on a semiconductor substrate; forming polysilicon over the whole surface of the insulating layer such that it fills the hole; forming a polysilicon plug in the hole by etching back a polysilicon; and heating the semiconductor substrate including the polysilicon plug within the insulating layer under a hydrogen atmosphere.

摘要翻译： 一种半导体器件，包括具有降低的接触电阻的多晶硅插塞及其制造工艺。 该方法包括在半导体衬底上的绝缘层中形成孔的步骤; 在绝缘层的整个表面上形成多晶硅，使其填充孔; 通过蚀刻多晶硅在孔中形成多晶硅插塞; 以及在氢气氛下将包括多晶硅插塞的半导体衬底加热到​​绝缘层内。

公开(公告)号：US06969649B2

公开(公告)日：2005-11-29

申请号：US10810884

申请日：2004-03-29

申请人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

发明人： Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Keizo Kawakita ,  Hideo Aoki ,  Toshikazu Kumai ,  Kazuhiko Saito ,  Michio Nishimura ,  Michio Tanaka ,  Katsuo Yuhara ,  Shinya Nishio ,  Toshiyuki Kaeriyama ,  Songsu Cho

IPC分类号： H01L21/8242 ,  H01L21/60 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

摘要翻译： 在一个实施例中，DRAM具有其上表面和侧表面被第一绝缘膜覆盖的多个字线，多个位线设置成与字线绝缘并横向于字线并被覆盖 具有第二绝缘膜和多个存储单元，每个存储单元设置在一个字线和一个位线之间的交点处，并且包括电容器和存储单元选择晶体管，其中用于在半导体区域和电容器之间以及半导体之间连接的接触孔 区域和位线形成为自对准，并且第二绝缘膜由电容率小于第一绝缘膜的介电常数的材料制成。