公开(公告)号：US20130082365A1

公开(公告)日：2013-04-04

申请号：US13251987

申请日：2011-10-03

申请人： WILLIAM E. BERNIER ,  BING DANG ,  MARIO J. INTERRANTE ,  JOHN U. KNICKERBOCKER ,  SON K. TRAN

发明人： WILLIAM E. BERNIER ,  BING DANG ,  MARIO J. INTERRANTE ,  JOHN U. KNICKERBOCKER ,  SON K. TRAN

IPC分类号： H01L23/552

CPC分类号： H01L24/81 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/552 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0655 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/19105 ,  H01L2924/00

摘要： A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.

摘要翻译： 插入器夹层结构包括顶部插入器和封装集成电路电子器件的底部插入器，其包括用于将器件附接到底部插入器的装置，以及将顶部插入件连接到底部插入器的互连结构。 除了底部插入器之外，顶部插入器还可以直接连接到芯片载体。 该结构提供了在小型化3D封装中防止静电放电（ESD），电磁干扰（EMI）和电磁导电（EMC））的器件的屏蔽和保护。

公开(公告)号：US20120187180A1

公开(公告)日：2012-07-26

申请号：US13422429

申请日：2012-03-16

申请人： Thomas E. LOMBARDI ,  Donald MERTE ,  Gregg B. MONJEAU ,  David L. QUESTAD ,  Son K. TRAN

发明人： Thomas E. LOMBARDI ,  Donald MERTE ,  Gregg B. MONJEAU ,  David L. QUESTAD ,  Son K. TRAN

IPC分类号： B23K31/02 ,  H01L21/58

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/40 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49894 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  Y10T29/41 ,  Y10T29/49117 ,  H01L2924/00

摘要： A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

公开(公告)号：US20120070940A1

公开(公告)日：2012-03-22

申请号：US12887809

申请日：2010-09-22

申请人： Thomas E. Lombardi ,  Donald Merte ,  Gregg B. Monjeau ,  David L. Questad ,  Son K. Tran

发明人： Thomas E. Lombardi ,  Donald Merte ,  Gregg B. Monjeau ,  David L. Questad ,  Son K. Tran

IPC分类号： H01L21/50 ,  B23K37/04

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/40 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49894 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  Y10T29/41 ,  Y10T29/49117 ,  H01L2924/00

摘要： A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

摘要翻译： 提供了一种形成芯片组件的固定装置和方法。 夹具组件包括具有开口尺寸以容纳安装在层压板上的芯片的第一板。 固定装置还包括通过至少一个机械紧固机构配合到第一板的第二板。 夹具组件还包括由第一板和第二板的相对表面限定的并由第一板和第二板中的至少一个的凸起台阶部限定的空间。 这个空间与开幕式一致。 该空间的尺寸和形状使得层压体被限制在空间内并且直接邻接第一板和第二板的阶梯部分和相对表面以被限制在X，Y和Z方向上。

公开(公告)号：US07119003B2

公开(公告)日：2006-10-10

申请号：US11148923

申请日：2005-06-08

申请人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

发明人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/351 ,  H05K3/3436 ,  H01L2924/00

摘要： A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.

公开(公告)号：US06739497B2

公开(公告)日：2004-05-25

申请号：US10145467

申请日：2002-05-13

申请人： Clément J. Fortin ,  Pierre M. Langevin ,  Son K. Tran ,  Michael B. Vincent

发明人： Clément J. Fortin ,  Pierre M. Langevin ,  Son K. Tran ,  Michael B. Vincent

IPC分类号： B23K3102

CPC分类号： H05K3/3442 ,  H01L21/563 ,  H01L2924/0002 ,  H05K3/284 ,  H05K3/305 ,  H05K3/3489 ,  H05K3/3494 ,  H05K2201/10636 ,  H05K2201/10977 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

摘要： An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into said encapsulant so that the electrical contacts make contact with said presoldered pads. Heat is applied to first activate said flux material and then reflow the solder on said presoldered pads to bond said SMD contacts to said presoldered pads. The reflow temperature is maintained for about 180 seconds during which time the resin solidifies. The resin encapsulant fills the space between substrate and SMD and forms fillets around the solder bonded contacts.

摘要翻译： 提供电子制造工艺和结构，用于在单个步骤中将分立的被动表面贴装器件（SMD）附接到衬底。 含有助焊剂材料的液体流动树脂密封剂被分配在基材上的预铸焊盘之间。 具有一对电触点的SMD被压入所述密封剂中，使得电触头与所述预铸焊盘接触。 施加热量以首先激活所述焊剂材料，然后回流所述预铸焊盘上的焊料，以将所述SMD触点接合到所述预铸焊盘。 回流温度保持约180秒，在此期间树脂固化。 树脂密封剂填充基板和SMD之间的空间，并在焊接接合点周围形成圆角。

公开(公告)号：US06713858B2

公开(公告)日：2004-03-30

申请号：US10404774

申请日：2003-03-31

申请人： Ramesh R. Kodnani ,  Luis J. Matienzo ,  Son K. Tran

发明人： Ramesh R. Kodnani ,  Luis J. Matienzo ,  Son K. Tran

IPC分类号： H01L2302

CPC分类号： H01L24/81 ,  C08G73/0611 ,  C08G73/0627 ,  H01L21/563 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14

摘要： An electronic module having enhanced adhesion at the chip passivation and underfill interface is disclosed. The surface of the chip passivation is chemically modified to a sufficient depth such that the cured passivation is more reactive. The modified surface is treated with a polyamine preferably having a cyclic amine group extending from a preferably aliphatic backbone. During reflow of the solder joints of the electronic module by heating, the modified passivation reacts with the polyamine at the amine functionality. Following underfill of the electronic module with a polymeric material, preferably an epoxy resin, the polyamine on the surface of the passivation reacts with the underfill material during curing of the underfill material. The resulting electronic module is more robust since the amine acts as a chemical anchoring site for both the modified passivation and the underfill material. A method of assembling an electronic module utilizing the polyamine treatment at the chip and wafer level is also disclosed.

摘要翻译： 公开了一种在芯片钝化和底部填充界面处具有增强的附着力的电子模块。 芯片钝化的表面被化学修饰到足够的深度，使得固化的钝化更具反应性。 改性表面用优选具有从优选脂肪族主链延伸的环状胺基团的多胺处理。 在通过加热回流电子模块的焊点时，改性的钝化剂在胺官能度下与多胺反应。 在具有聚合材料，优选环氧树脂的电子模块的底部填充之后，钝化剂表面上的多胺在底部填充材料的固化期间与底部填充材料反应。 所得到的电子模块更加坚固，因为胺用作修饰的钝化和底部填充材料的化学锚定位点。 还公开了利用芯片和晶片级的多胺处理来组装电子模块的方法。

公开(公告)号：US06306683B1

公开(公告)日：2001-10-23

申请号：US09526569

申请日：2000-03-16

申请人： Jean Dery ,  Frank D. Egitto ,  Luis J. Matienzo ,  Charles Ouellet ,  Luc Ouellet ,  David L. Questad ,  William J. Rudik ,  Son K. Tran

发明人： Jean Dery ,  Frank D. Egitto ,  Luis J. Matienzo ,  Charles Ouellet ,  Luc Ouellet ,  David L. Questad ,  William J. Rudik ,  Son K. Tran

IPC分类号： H01L2144

CPC分类号： H01L24/28 ,  H01L21/563 ,  H01L24/45 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10S438/959 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/48

摘要： A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O2 plasma or a microwave-generated Ar and N2O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treat with the plasma before they are joined to one another. The plasma treatment improves adhesion between the encapsulant and the IC chip, and between the encapsulant and the chip carrier.

摘要翻译： 一种用于形成板上倒装芯片组件的方法。 具有聚酰亚胺钝化层的集成电路（IC）芯片通过将IC芯片上的多个接触焊盘电连接到芯片载体上的相应触点的多个焊料凸块而接合到芯片载体。 在钝化层的表面和芯片载体的表面之间形成空间。 施加等离子体以化学改性芯片载体的表面和IC芯片的钝化层，基本上不使钝化层的表面变粗糙。 等离子体是O2等离子体或微波产生的Ar和N2O等离子体。 应用底部填充密封材料填充空间。 等离子体处理可以在接合步骤之后进行。 然后，同时用等离子体处理芯片和芯片载体。 或者，IC芯片和芯片载体可以在彼此接合之前用等离子体处理。 等离子体处理改善了密封剂和IC芯片之间以及密封剂和芯片载体之间的粘合性。

公开(公告)号：US6074895A

公开(公告)日：2000-06-13

申请号：US936032

申请日：1997-09-23

申请人： Jean Dery ,  Frank D. Egitto ,  Luis J. Matienzo ,  Charles Ouellet ,  Luc Ouellet ,  David L. Questad ,  William J. Rudik ,  Son K. Tran

发明人： Jean Dery ,  Frank D. Egitto ,  Luis J. Matienzo ,  Charles Ouellet ,  Luc Ouellet ,  David L. Questad ,  William J. Rudik ,  Son K. Tran

IPC分类号： H01L21/56 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/28 ,  H01L21/563 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L24/45 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  Y10S438/959

摘要： A method for forming a flip-chip-on-board assembly. An integrated circuit (IC) chip having a polyimide passivation layer is joined to a chip carrier via a plurality of solder bumps which electrically connect a plurality of contact pads on the IC chip to corresponding contacts on the chip carrier. A space is formed between a surface of the passivation layer and a surface of the chip carrier. A plasma is applied, to chemically modify the a surface of the chip carrier and the passivation layer of the IC chip substantially without roughening the surface of the passivation layer. The plasma is either an O.sub.2 plasma or a microwave-generated Ar and N.sub.2 O plasma. An underfill encapsulant material is applied to fill the space. The plasma treatment may be performed after the step of joining. Then, the chip and chip carrier are treated with the plasma simultaneously. Alternatively, the IC chip and chip carrier may be treated with the plasma before they are joined to one another. The plasma treatment improves adhesion between the encapsulant and the IC chip, and between the encapsulant and the chip carrier.

摘要翻译： 一种用于形成板上倒装芯片组件的方法。 具有聚酰亚胺钝化层的集成电路（IC）芯片通过将IC芯片上的多个接触焊盘电连接到芯片载体上的相应触点的多个焊料凸块而接合到芯片载体。 在钝化层的表面和芯片载体的表面之间形成空间。 施加等离子体，以化学改性芯片载体的表面和IC芯片的钝化层，基本上不使钝化层的表面变粗糙。 等离子体是O2等离子体或微波产生的Ar和N2O等离子体。 应用底部填充密封材料填充空间。 等离子体处理可以在接合步骤之后进行。 然后，同时用等离子体处理芯片和芯片载体。 或者，IC芯片和芯片载体可以在彼此接合之前用等离子体处理。 等离子体处理改善了密封剂和IC芯片之间以及密封剂和芯片载体之间的粘合性。

公开(公告)号：US08759151B2

公开(公告)日：2014-06-24

申请号：US13422429

申请日：2012-03-16

申请人： Thomas E. Lombardi ,  Donald Merte ,  Gregg B. Monjeau ,  David L. Questad ,  Son K. Tran

发明人： Thomas E. Lombardi ,  Donald Merte ,  Gregg B. Monjeau ,  David L. Questad ,  Son K. Tran

IPC分类号： H01L21/00

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K3/087 ,  B23K2101/40 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/49894 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  Y10T29/41 ,  Y10T29/49117 ,  H01L2924/00

摘要： A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

摘要翻译： 提供了一种形成芯片组件的固定装置和方法。 夹具组件包括具有开口尺寸以容纳安装在层压板上的芯片的第一板。 固定装置还包括通过至少一个机械紧固机构配合到第一板的第二板。 夹具组件还包括由第一板和第二板的相对表面限定的并由第一板和第二板中的至少一个的凸起台阶部限定的空间。 这个空间与开幕式一致。 该空间的尺寸和形状使得层压体被限制在空间内并且直接邻接第一板和第二板的阶梯部分和相对表面以被限制在X，Y和Z方向上。

公开(公告)号：US07067916B2

公开(公告)日：2006-06-27

申请号：US09885853

申请日：2001-06-20

申请人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

发明人： William E. Bernier ,  Charles F. Carey ,  Eberhard B. Gramatzki ,  Thomas R. Homa ,  Eric A. Johnson ,  Pierre Langevin ,  Irving Memis ,  Son K. Tran ,  Robert F. White

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/351 ,  H05K3/3436 ,  H01L2924/00

摘要： A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.