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公开(公告)号:US20110089562A1
公开(公告)日:2011-04-21
申请号:US12960717
申请日:2010-12-06
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L23/485
CPC分类号: H01L23/49816 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L2224/023 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05541 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11 , H01L2224/11334 , H01L2224/1147 , H01L2224/1148 , H01L2224/1191 , H01L2224/13 , H01L2224/13005 , H01L2224/13006 , H01L2224/13022 , H01L2224/13023 , H01L2224/13027 , H01L2224/13099 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/207 , H01L2224/05552 , H01L2924/00
摘要: A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
摘要翻译: 一种半导体器件,包括具有电路元件的半导体衬底和形成在一个表面上的电极焊盘。 该表面被具有在电极焊盘上方开口的电介质层覆盖。 金属层被包括在电介质层上并被图案化以形成具有通向电极焊盘的迹线的导电图案。 包括保护层,具有暴露部分导电图案的开口。 每个开口由诸如焊料凸点的电极覆盖,焊料凸块通过导电图案电连接到电极焊盘之一。 因此可以减小作为半导体器件的封装的保护层的厚度。 保护层可以由感光材料形成,从而简化了用于电极的开口的形成。
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公开(公告)号:US07884008B2
公开(公告)日:2011-02-08
申请号:US12489544
申请日:2009-06-23
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
CPC分类号: H01L23/49816 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L2224/023 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05541 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/11 , H01L2224/11334 , H01L2224/1147 , H01L2224/1148 , H01L2224/1191 , H01L2224/13 , H01L2224/13005 , H01L2224/13006 , H01L2224/13022 , H01L2224/13023 , H01L2224/13027 , H01L2224/13099 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/207 , H01L2224/05552 , H01L2924/00
摘要: A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.
摘要翻译: 一种形成半导体器件的方法,该半导体器件包括具有形成在一个表面上的电路元件和电极焊盘的半导体衬底。 该表面被具有在电极焊盘上方开口的电介质层覆盖。 金属层沉积在电介质层上并被图案化以形成具有通向电极焊盘的迹线的导电图案。 形成具有露出导电图案的一部分的开口的保护层。 每个开口由诸如焊料凸点的电极覆盖,焊料凸块通过导电图案电连接到电极焊盘之一。 该方法能够减小作为半导体器件的封装的保护层的厚度。 保护层可以由感光材料形成,从而简化了用于电极的开口的形成。
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公开(公告)号:US07282800B2
公开(公告)日:2007-10-16
申请号:US10902467
申请日:2004-07-30
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L23/52
CPC分类号: H01L24/12 , H01L23/3114 , H01L23/525 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05569 , H01L2224/05647 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/04953 , H01L2924/12044 , H01L2924/00 , H01L2924/00014
摘要: The present invention provides a semiconductor device capable of improving productivity while maintaining electrical characteristics, and a manufacturing method thereof. One characteristic point of the present invention is that a plating processing condition (A) for forming a metal wiring layer (redistribution wiring) corresponding to a first conductive layer and a plating processing condition (B) for forming a post electrode corresponding to a second conductive layer are made different from each other.
摘要翻译: 本发明提供一种能够在保持电气特性的同时提高生产率的半导体器件及其制造方法。 本发明的一个特征在于,用于形成对应于第一导电层的金属布线层(再分配布线)的电镀处理条件(A)和用于形成对应于第二导电的电极的电镀处理条件(B) 层被制成彼此不同。
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公开(公告)号:US20060278973A1
公开(公告)日:2006-12-14
申请号:US11508212
申请日:2006-08-23
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L23/053
CPC分类号: H01L24/19 , H01L23/3135 , H01L23/5389 , H01L24/97 , H01L2224/04105 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15787 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要: A semiconductor device comprises: a base; a semiconductor chip provided on the base which includes a first main surface 20a on which a plurality of electrode pads is provided, a surface protecting film provided on the first main surface, a second main surface which opposes the first main surface, and a plurality of side surfaces between the surface of the surface protecting film and the second main surface; an insulating extension portion formed so as to surround the side surfaces of the semiconductor chip; a plurality of wiring patterns electrically connected to the electrode pads, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed on the wiring patterns such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided on the wiring patterns in a region including the upper side of the extension portion.
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公开(公告)号:US08110923B2
公开(公告)日:2012-02-07
申请号:US12851566
申请日:2010-08-06
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L23/48
CPC分类号: H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2223/54406 , H01L2223/54433 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2224/0401 , H01L2224/16 , H01L2924/01078 , H01L2924/14 , H01L2924/00
摘要: An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously.
摘要翻译: 提供了一种改进的半导体器件的制造方法。 该方法包括制备具有集成电路和连接焊盘的半导体衬底。 该方法还包括在半导体衬底上形成电介质膜。 该方法还包括在电介质膜上形成具有预定图案的连接线,使得连接线电连接到连接焊盘。 该方法还包括形成表面树脂层以部分地覆盖连接线。 该方法还包括在暴露的连接线上形成金属膜。 该方法还包括形成具有通孔的显示单元,以在与表面树脂层上的半导体衬底的中心区域对应的区域中呈现识别信息。 金属膜的形成和显示单元的形成同时进行。
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公开(公告)号:US20100283150A1
公开(公告)日:2010-11-11
申请号:US12805169
申请日:2010-07-15
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L23/49 , H01L23/498 , H01L23/48
CPC分类号: H01L23/3114 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/02313 , H01L2224/0401 , H01L2224/05599 , H01L2224/11334 , H01L2224/1147 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2224/13099
摘要: The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which exposes each area for forming a redistribution wiring, over the bedding metal layer, forming a redistribution wiring connected to the electrode pad and extending in an electrode forming area for a post electrode with the first resist mask as a mask, removing the first resist mask by a dissolving solution to expose each area excluding the electrode forming area for the redistribution wiring and forming a second resist mask disposed with being separated from each side surface of the redistribution wiring, forming a redistribution wiring protective metal film over upper and side surfaces of the exposed redistribution wiring with the second resist mask as a mask, removing the second resist mask by a dissolving solution, attaching a dry film over the semiconductor wafer and exposing the electrode forming area lying over the redistribution wiring, forming a post electrode in the electrode forming area with the dry film as a mask, removing the dry film by a removal solvent, and removing the redistribution wiring protective metal film after the removal of the dry film.
摘要翻译: 本发明提供一种形成半导体器件的方法,其包括以下步骤:制备半导体晶片,该半导体晶片包括形成在半导体衬底中的电极焊盘,形成有通孔的绝缘膜和层压金属层,形成第一 抗蚀剂掩模,其在床垫金属层上暴露用于形成再分布布线的每个区域,形成连接到电极焊盘的再分配布线,并且在第一抗蚀剂掩模作为掩模的用于柱状电极的电极形成区域中延伸,去除第一 通过溶解溶液防止掩模暴露除了用于再分配布线的电极形成区域之外的各个区域,并且形成设置为与再分布布线的每个侧表面分离的第二抗蚀剂掩模,在重新分布布线保护金属膜的上表面和侧表面上形成 以第二抗蚀剂掩模为掩模的曝光再分配布线,除去s 通过溶解溶液涂覆抗蚀剂掩模,在半导体晶片上附着干膜,暴露位于再分布布线上的电极形成区域,在干燥膜作为掩模的电极形成区域中形成柱状电极,通过 去除溶剂,并且在除去干膜之后除去再分布布线保护金属膜。
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公开(公告)号:US07741705B2
公开(公告)日:2010-06-22
申请号:US11889830
申请日:2007-08-16
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L23/495
CPC分类号: H01L23/3114 , H01L21/2885 , H01L21/76822 , H01L21/76885 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/02351 , H01L2224/0401 , H01L2224/05569 , H01L2224/05571 , H01L2224/05599 , H01L2224/1147 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1305 , H01L2224/13099 , H01L2924/00
摘要: A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.
摘要翻译: 半导体器件包括具有内部电路的半导体衬底; 与内部电路电连接的电极焊盘; 绝缘膜,具有使电极焊盘露出的通孔; 以及形成在绝缘膜上并电连接到电极焊盘的再分配布线图案。 半导体器件还包括在重分配布线图案周围并与其相邻的绝缘膜中形成的凹槽。
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公开(公告)号:US07534664B2
公开(公告)日:2009-05-19
申请号:US11902757
申请日:2007-09-25
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L21/00
CPC分类号: H01L24/12 , H01L23/3114 , H01L23/525 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05569 , H01L2224/05647 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/04953 , H01L2924/12044 , H01L2924/00 , H01L2924/00014
摘要: The present invention provides a semiconductor device capable of improving productivity while maintaining electrical characteristics, and a manufacturing method thereof. One characteristic point of the present invention is that a plating processing condition (A) for forming a metal wiring layer (redistribution wiring) corresponding to a first conductive layer and a plating processing condition (B) for forming a post electrode corresponding to a second conductive layer are made different from each other.
摘要翻译: 本发明提供一种能够在保持电气特性的同时提高生产率的半导体器件及其制造方法。 本发明的一个特征在于,用于形成对应于第一导电层的金属布线层(再分配布线)的电镀处理条件(A)和用于形成对应于第二导电的电极的电镀处理条件(B) 层被制成彼此不同。
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公开(公告)号:US20080054479A1
公开(公告)日:2008-03-06
申请号:US11889830
申请日:2007-08-16
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
CPC分类号: H01L23/3114 , H01L21/2885 , H01L21/76822 , H01L21/76885 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/02351 , H01L2224/0401 , H01L2224/05569 , H01L2224/05571 , H01L2224/05599 , H01L2224/1147 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1305 , H01L2224/13099 , H01L2924/00
摘要: A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern.
摘要翻译: 半导体器件包括具有内部电路的半导体衬底; 与内部电路电连接的电极焊盘; 绝缘膜,具有使电极焊盘露出的通孔; 以及形成在绝缘膜上并电连接到电极焊盘的再分配布线图案。 半导体器件还包括在重分配布线图案周围并与其相邻的绝缘膜中形成的凹槽。
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公开(公告)号:US08274154B2
公开(公告)日:2012-09-25
申请号:US12926662
申请日:2010-12-02
申请人: Kiyonori Watanabe
发明人: Kiyonori Watanabe
IPC分类号: H01L21/44
CPC分类号: H01L24/11 , H01L23/3171 , H01L2224/023 , H01L2224/0401 , H01L2224/051 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/056 , H01L2224/05644 , H01L2224/05647 , H01L2224/13023 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要: A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion.
摘要翻译: 提供能够防止接合层剥离和裂纹发生在再布线层的边缘部附近的半导体装置。 半导体器件包括半导体衬底,形成在半导体衬底上的电极焊盘,形成在半导体衬底上的第一绝缘膜,具有暴露电极焊盘的第一孔,形成在电极焊盘上的第一导体膜和第一绝缘膜 电连接到第一导体膜的外部电极和覆盖第一导体膜和第一绝缘膜的密封树脂。 第一导体膜包括多个铜层,这些铜层被堆叠成使得第一导体膜的外边缘部分具有台阶部分。
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