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    Programmable polysilicon gate array base cell architecture
    5.
    发明授权
    Programmable polysilicon gate array base cell architecture 失效
    可编程多晶硅门阵列基体结构

    公开(公告)号：US5917207A

    公开(公告)日：1999-06-29

    申请号：US800663

    申请日：1997-02-14

    申请人： Michael J. Colwell ,  Teh-Kuin Lee ,  Jane C.T. Chiu ,  Abraham F. Yee ,  Stanley Wen-Chin Yeh ,  Gobi R. Padmanabhan

    发明人： Michael J. Colwell ,  Teh-Kuin Lee ,  Jane C.T. Chiu ,  Abraham F. Yee ,  Stanley Wen-Chin Yeh ,  Gobi R. Padmanabhan

    IPC分类号： H01L21/768 ,  H01L27/118 ,  H01L21/82 ,  H01L27/04 ,  H01L27/10

    CPC分类号： H01L21/76892 ,  H01L27/11807

    摘要： A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell des the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

    摘要翻译： 公开了具有可编程多晶硅层的栅极阵列，其可以用作MOS晶体管的栅电极和用于栅电极之间的一些连接的布线线。 栅极阵列结构形成在半导体衬底上并且具有位于结构的芯部区域中的相同基底单元的阵列。 每个这样的基站具有以下元件：（1）多个晶体管，每个晶体管包括栅电极; 以及（2）形成在所述基板上的一个或多个栅极连接条，并且电连接所述晶体管中的两个或更多个的所选择的栅电极。 优选地，栅极连接条由与所选择的栅电极（例如，多晶硅）相同的材料制成并与其一体地连接。 栅极连接条可以被图案化（即被编程）以在各种晶体管的栅极之间形成衬底层布线。

    Method and system for controlling a semiconductor fabrication process
    6.
    发明授权
    Method and system for controlling a semiconductor fabrication process 有权
    用于控制半导体制造工艺的方法和系统

    公开(公告)号：US07964422B1

    公开(公告)日：2011-06-21

    申请号：US11264122

    申请日：2005-11-01

    申请人： Abraham F. Yee

    发明人： Abraham F. Yee

    IPC分类号： H01L21/00

    CPC分类号： H01L21/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.

    摘要翻译： 一种用于控制半导体制造工艺的方法包括以下步骤：分析与制造工艺中的中间工艺步骤相关的工艺数据，并根据工艺数据调整对应于金属层的金属层参数。

    HIGH DENSITY 3D PACKAGE
    7.
    发明申请
    HIGH DENSITY 3D PACKAGE 审中-公开
    高密度3D包装

    公开(公告)号：US20130277855A1

    公开(公告)日：2013-10-24

    申请号：US13455080

    申请日：2012-04-24

    申请人： Terry (Teckgyu) Kang ,  Abraham F. Yee

    发明人： Terry (Teckgyu) Kang ,  Abraham F. Yee

    IPC分类号： H01L23/48 ,  H01L23/12 ,  H01L21/56 ,  H01L21/58

    CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/18 ,  H01L2023/4062 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/014

    摘要： Embodiments of the present provide an integrated circuit system, which includes an interposer having a plurality of electrical conductive vias running through the interposer, one or more high-power chips mounted on a first surface of the interposer, wherein the one or more high-power chips generate at least 10 W of heat during normal operation, one or more low-power chips mounted on a second surface of the interposer, wherein the one or more low-power chips generate less than 5 W of heat during normal operation, and the first surface and the second surface are opposite and substantially parallel to each other, and an encapsulating material formed over and configured to encapsulate the one or more high-power chips and the one or more low-power chips. Since low-power chips and high-power chips are respectively mounted on front side and back side of the interposer, the footprint of the interposer and manufacturing cost associated therewith is reduced.

    摘要翻译： 本发明的实施例提供一种集成电路系统，其包括具有穿过插入件的多个导电通孔的插入器，安装在插入器的第一表面上的一个或多个高功率芯片，其中所述一个或多个高功率 芯片在正常操作期间产生至少10W的热量，一个或多个低功率芯片安装在插入器的第二表面上，其中一个或多个低功率芯片在正常操作期间产生小于5W的热量， 第一表面和第二表面彼此相对并且基本上彼此平行;以及封装材料，形成在一个或多个高功率芯片和一个或多个低功率芯片上并构造成封装一个或多个高功率芯片。 由于低功率芯片和大功率芯片分别安装在插入器的前侧和后侧，因此降低了插入器的占地面积和与之相关的制造成本。

    Method of fabricating a programmable polysilicon gate array base cell structure
    8.
    发明授权
    Method of fabricating a programmable polysilicon gate array base cell structure 失效
    制造可编程多晶硅门阵列基体结构的方法

    公开(公告)号：US5691218A

    公开(公告)日：1997-11-25

    申请号：US613038

    申请日：1996-03-08

    申请人： Michael J. Colwell ,  Teh-Kuin Lee ,  Jane C.T. Chiu ,  Abraham F. Yee ,  Stanley Yeh ,  Gobi R. Padmanabhan

    发明人： Michael J. Colwell ,  Teh-Kuin Lee ,  Jane C.T. Chiu ,  Abraham F. Yee ,  Stanley Yeh ,  Gobi R. Padmanabhan

    IPC分类号： H01L21/768 ,  H01L27/118 ,  H01L21/265

    CPC分类号： H01L21/76892 ,  H01L27/11807

    摘要： A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell includes the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

    摘要翻译： 公开了具有可编程多晶硅层的栅极阵列，其可以用作MOS晶体管的栅电极和用于栅电极之间的一些连接的布线线。 栅极阵列结构形成在半导体衬底上并且具有位于结构的芯部区域中的相同基底单元的阵列。 每个这样的基电池包括以下元件：（1）多个晶体管，每个晶体管包括栅电极; 以及（2）形成在所述基板上的一个或多个栅极连接条，并且电连接所述晶体管中的两个或更多个的所选择的栅电极。 优选地，栅极连接条由与所选择的栅电极（例如，多晶硅）相同的材料制成并与其一体地连接。 栅极连接条可以被图案化（即被编程）以在各种晶体管的栅极之间形成衬底层布线。

    Method and system for controlling a semiconductor fabrication process
    10.
    发明授权
    Method and system for controlling a semiconductor fabrication process 有权
    用于控制半导体制造工艺的方法和系统

    公开(公告)号：US09570284B1

    公开(公告)日：2017-02-14

    申请号：US12649207

    申请日：2009-12-29

    申请人： Abraham F. Yee

    发明人： Abraham F. Yee

    IPC分类号： H01L21/00

    CPC分类号： H01L21/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.

    摘要翻译： 一种用于控制半导体制造工艺的方法包括以下步骤：分析与制造工艺中的中间工艺步骤相关的工艺数据，并根据工艺数据调整对应于金属层的金属层参数。