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公开(公告)号：US06753216B2
公开(公告)日：2004-06-22
申请号：US10285059
申请日：2002-10-31
IPC分类号： H01L218238
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795 , H01L29/78603 , H01L29/78621
摘要： A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).
摘要翻译： 一种在衬底（102）上形成电介质结构（106）的半导体制造工艺和结构。 然后沉积和处理硅以形成包封电介质结构（106）并与衬底（102）物理和电气隔离的晶体硅壁（118）。 在硅壁（118）的至少两个表面上形成栅极电介质膜（130），并且在栅极电介质（130）上形成栅电极膜（132）。 然后对栅极电极膜（132）进行构图，然后进行常规的源极/漏极注入处理。 设置在栅电极（140）的任一侧的硅壁（118）的部分然后可以接触以形成源极/漏极结构（150）。 以这种方式，由栅电极（140）覆盖的硅壁（118）的部分包括具有由栅电极（140）控制的多个表面的晶体管沟道区。
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2.发明申请公开(公告)号：US20050101069A1
公开(公告)日：2005-05-12
申请号：US10695163
申请日：2003-10-28
申请人： Leo Mathew , Rode Mora , Bich-Yen Nguyen , Tab Stephens , Anne Vandooren
发明人： Leo Mathew , Rode Mora , Bich-Yen Nguyen , Tab Stephens , Anne Vandooren
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/00 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/823468 , H01L29/66628 , H01L29/66795 , H01L29/66818
摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.
摘要翻译： 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。
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公开(公告)号：US06509609B1
公开(公告)日：2003-01-21
申请号：US09884345
申请日：2001-06-18
IPC分类号： H01L2978
CPC分类号： H01L29/66643 , H01L21/823437 , H01L21/823828 , H01L29/6656 , H01L29/66621 , H01L29/7834 , H01L29/7839
摘要： A grooved channel Schottky contacted MOSFET has asymmetric source and drain regions. The MOSFET includes an undoped silicon substrate with a background doping concentration of less than about 1017 cm−3. A grooved channel is formed in a first surface of the substrate. A first metal silicide material is formed in a first side of the grooved channel, forming a source region, and a second metal silicide material is formed on a second side of the grooved channel, forming a drain region. A metal gate is formed in the grooved channel. The grooved structure allows the off-state current to be reduced to less than 50 pA/&mgr;m. Further, the feature size can be scaled down to 10 nm without strong short-channel effects (DIBL
摘要翻译： 沟槽沟道肖特基接触MOSFET具有不对称的源极和漏极区域。 MOSFET包括背景掺杂浓度小于约1017cm-3的未掺杂硅衬底。 在基板的第一表面中形成开槽通道。 第一金属硅化物材料形成在带槽沟道的第一侧，形成源极区，并且第二金属硅化物材料形成在带槽沟道的第二侧上，形成漏区。 在沟槽通道中形成金属门。 带槽结构允许关断状态电流降低到小于50pA / mum。 此外，特征尺寸可以缩小到10nm，而没有强的短信道效应（DIBL <0.063），并且门延迟（CV / I）降低到2.4ps。
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4.发明授权公开(公告)号：US06949455B2
公开(公告)日：2005-09-27
申请号：US10677070
申请日：2003-10-01
申请人： Daniel Thanh-Khac Pham , Bich-Yen Nguyen , James K. Schaeffer , Melissa O. Zavala , Sherry G. Straub , Kimberly G. Reid , Marc Rossow , James P. Geren
发明人： Daniel Thanh-Khac Pham , Bich-Yen Nguyen , James K. Schaeffer , Melissa O. Zavala , Sherry G. Straub , Kimberly G. Reid , Marc Rossow , James P. Geren
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4933 , H01L29/51
摘要： A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
摘要翻译： 用于提供具有至少两种不同功函数的晶体管栅极的方法利用两种不同金属在不同时间的硅化，一个栅极的硅化，另一个的硅化，或使用具有两个不同掺杂硅结构的单一金属的硅化。 因此，避免了与同时进行两种不同金属的硅化相关的问题。 如果两种金属具有明显不同的硅化物温度，则由于必须也经历用其它金属进行硅化所需的较高温度，具有较低温度硅化的温度可能会显着降低性能。
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公开(公告)号：US20060170016A1
公开(公告)日：2006-08-03
申请号：US11047946
申请日：2005-02-01
申请人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66659 , H01L29/7843
摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
摘要翻译： 提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。 分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。 在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层， 或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。
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公开(公告)号：US06838322B2
公开(公告)日：2005-01-04
申请号：US10427577
申请日：2003-05-01
申请人： Daniel T. Pham , Alexander L. Barr , Leo Mathew , Bich-Yen Nguyen , Anne M. Vandooren , Ted R. White
发明人： Daniel T. Pham , Alexander L. Barr , Leo Mathew , Bich-Yen Nguyen , Anne M. Vandooren , Ted R. White
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00 , H01L21/20 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a polysilicon FinFET (10) or other thin film transistor structure includes forming an insulative layer (12) over a semiconductor substrate (14). An amorphous silicon layer (32) forms over the insulative layer (12). A silicon germanium seed layer (44) forms in association with the amorphous silicon layer (32) for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (32). During the annealing step, silicon germanium seed layer (44), together with silicon germanium layer (34), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (16), drain (18), and channel (20) regions are formed within the polysilicon layer. A double-gated region (24) forms in association with source (16), drain (18), and channel (20) to produce polysilicon FinFET (10).
摘要翻译： 一种用于形成多晶硅FinFET（10）或其它薄膜晶体管结构的方法包括在半导体衬底（14）上形成绝缘层（12）。 在绝缘层（12）上形成非晶硅层（32）。 与用于控制硅晶粒生长的非晶硅层（32）相关联地形成硅锗籽晶层（44）。 多晶硅层由退火非晶硅层（32）引起。 在退火步骤期间，硅锗籽晶层（44）与硅锗层（34）一起催化硅重结晶以促进生长较大的晶粒以及所得多晶硅层内的较少的晶界。 源极（16），漏极（18）和沟道（20）区域形成在多晶硅层内。 与源极（16），漏极（18）和沟道（20）相关联地形成双门控区域（24）以产生多晶硅FinFET（10）。
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公开(公告)号：US07803670B2
公开(公告)日：2010-09-28
申请号：US11458902
申请日：2006-07-20
申请人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
发明人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
IPC分类号： H01L21/00
CPC分类号： H01L21/845 , H01L21/76264 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g., 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
摘要翻译： 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。
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公开(公告)号：US07585735B2
公开(公告)日：2009-09-08
申请号：US11047946
申请日：2005-02-01
申请人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Leo Mathew , Yang Du , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8234
CPC分类号： H01L29/4983 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66659 , H01L29/7843
摘要： A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (162); and/or (d) the device has an oxide layer (160) disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.
摘要翻译： 提供一种形成半导体器件的方法，其中设置有其上设置有栅介质层（106）的衬底（102），并且在栅极介电层上形成具有第一和第二侧壁的栅电极（116）。 分别在第一和第二侧壁附近形成第一（146）和第二（150）延伸间隔结构。 在所得装置中：（a）第一和第二延伸间隔结构具有不同的尺寸; （b）第一和第二延伸间隔结构包括第一和第二不同材料; （c）该器件具有不对称的源极/漏极延伸部分（162）; 和/或（d）所述器件具有设置在所述第一延伸间隔物结构和所述栅电极之间的氧化物层（160），以及（i）所述器件在所述第二延伸间隔物结构和所述栅电极之间没有设置介电层， 或者（ii）该器件具有设置在第二延伸间隔物结构和栅极之间的第二介电层，并且第一介电层基本上比第二介电层更厚。
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9.发明授权Confined spacers for double gate transistor semiconductor fabrication process 有权用于双栅晶体管半导体制造工艺的密封间隔物公开(公告)号：US06951783B2
公开(公告)日：2005-10-04
申请号：US10695163
申请日：2003-10-28
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823437 , H01L21/823468 , H01L29/66628 , H01L29/66795 , H01L29/66818
摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.
摘要翻译： 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅极电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。
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公开(公告)号：US20080020515A1
公开(公告)日：2008-01-24
申请号：US11458902
申请日：2006-07-20
申请人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
发明人： Ted R. White , Leo Mathew , Bich-Yen Nguyen , Zhonghai Shi , Voon-Yew Thean , Mariam G. Sadaka
IPC分类号： H01L21/00
CPC分类号： H01L21/845 , H01L21/76264 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).
摘要翻译： 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。
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