公开(公告)号：US20210202316A1

公开(公告)日：2021-07-01

申请号：US16728374

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Suresh K. Upadhyayula ,  Thiam Chye Lim

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/67 ,  H01L21/687

Abstract: A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices.

公开(公告)号：US20170256528A1

公开(公告)日：2017-09-07

申请号：US15602759

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Thiam Chye Lim

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

Abstract: Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. The laterally offset semiconductor dice may be electrically connected to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.

公开(公告)号：US20170012031A1

公开(公告)日：2017-01-12

申请号：US14792970

申请日：2015-07-07

Applicant: Micron Technology, Inc.

Inventor： Thiam Chye Lim

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/31 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

Abstract: Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each semiconductor-device-package location may include at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the dice and extending between adjacent semiconductor-device-package locations. Electrically conductive traces may extend over active surfaces of the dice and laterally beyond peripheries of the dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric molding material. Semiconductor dice may be stacked on a side of at least some semiconductor-device-package locations of the fan out wafer opposite the electrically conductive traces. The stacks of semiconductor dice may be electrically connected to electrically conductive vias of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.

Abstract translation: 制造半导体器件封装的方法可以包括提供包括半导体器件封装位置的扇出晶片。 每个半导体器件封装位置可以包括至少两个相互间隔的半导体管芯和横向围绕每个管芯并在相邻的半导体器件封装位置之间延伸的电介质材料。 导电迹线可以在骰子的有效表面上延伸，并且横向延伸超过电介质材料上的骰子的周边，从导电迹线延伸通过电介质成型材料的导电通孔的位置。 半导体管芯可以堆叠在与导电迹线相对的扇形晶片的至少一些半导体器件封装位置的一侧。 半导体管芯的堆叠可以电连接到至少一些半导体器件封装位置的导电通孔。 半导体器件封装位置，其上具有半导体管芯的堆叠可以从扇形晶片上分离出来。

公开(公告)号：US11282746B2

公开(公告)日：2022-03-22

申请号：US16728374

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Suresh K. Upadhyayula ,  Thiam Chye Lim

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/687 ,  H01L21/67

Abstract: A method of manufacturing a microelectronic device may include forming a wiring layer on a first surface of a wafer. The method may also include forming a modified layer along separation regions for each microelectronic device of the wafer by focusing a laser on an inside portion of the wafer. The method may also include removing material from the second surface of the wafer. The wafer may be cooled to a temperature where a low dielectric constant layer extending across the separation regions is brittle while the material is removed from the second surface of the wafer. The method may further include separating the wafer along the separation region to form separate microelectronic devices.

公开(公告)号：US10115715B2

公开(公告)日：2018-10-30

申请号：US15602759

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Thiam Chye Lim

IPC: H01L23/49 ,  H01L23/488 ,  H01L21/50 ,  H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10

Abstract: Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level. Laterally offset semiconductor dice may be stacked at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice. The laterally offset semiconductor dice may be electrically connected to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.

公开(公告)号：US09673183B2

公开(公告)日：2017-06-06

申请号：US14792970

申请日：2015-07-07

Applicant: Micron Technology, Inc.

Inventor： Thiam Chye Lim

IPC: H01L23/34 ,  H01L23/48 ,  H01L21/50 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

Abstract: Methods of making semiconductor device packages may involve providing a fan out wafer including semiconductor-device-package locations. Each semiconductor-device-package location may include at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the dice and extending between adjacent semiconductor-device-package locations. Electrically conductive traces may extend over active surfaces of the dice and laterally beyond peripheries of the dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric molding material. Semiconductor dice may be stacked on a side of at least some semiconductor-device-package locations of the fan out wafer opposite the electrically conductive traces. The stacks of semiconductor dice may be electrically connected to electrically conductive vias of the at least some semiconductor-device-package locations. The semiconductor-device-package locations having stacks of semiconductor dice thereon may be singulated from the fan out wafer.

公开(公告)号：US20130154117A1

公开(公告)日：2013-06-20

申请号：US13765077

申请日：2013-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hock Chuan Tan ,  Thiam Chye Lim ,  Victor Cher Khng Tan ,  Chee Peng Neo ,  Michael Kian Shing Tan ,  Beng Chye Chew ,  Cheng Poh Pour

IPC: H01L25/07 ,  H01L25/00

CPC classification number: H01L25/074 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/86 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/50 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Die assemblies may include a first die abutting a substrate comprising a recess adjacent to the substrate. An adhesive element may be contained within the recess to attach the first die to the substrate. A height of the adhesive element may not contribute to an overall height of the die assembly. In some embodiments, a second die comprising a non-rectangular cross-sectional shape may be situated on the first die. Die assemblies ma also comprise a first die on a substrate and comprising a cavity on a side of the first die opposing a side on which the support substrate is located. A second die may be at least partially disposed in the cavity. Die assemblies may also comprise a first die secured to a substrate and partially inserted into a recess of a second die on a side opposing a side on which the substrate is located.

Abstract translation: 模具组件可以包括邻接基板的第一模具，该基板包括与基板相邻的凹部。 凹部中可以包含粘合元件以将第一模具附接到基板。 粘合元件的高度可能不会影响模具组件的整体高度。 在一些实施例中，包括非矩形横截面形状的第二模具可以位于第一模具上。 模具组件还包括在基板上的第一模具，并且在第一模具的一侧上包括与支撑基板所在的一侧相对的空腔。 第二模具可以至少部分地设置在空腔中。 模具组件还可以包括固定到基板并且部分地插入到与基板所在的一侧相对的一侧上的第二模具的凹部中的第一模具。