公开(公告)号：US5518940A

公开(公告)日：1996-05-21

申请号：US368906

申请日：1995-01-05

申请人： Mari Hodate ,  Norihisa Matsumoto ,  Kohji Ohgata ,  Tamotsu Wada ,  Ken-iti Yanai ,  Ken-ichi Oki ,  Yasuyoshi Mishima ,  Michiko Takei ,  Tatsuya Kakehi ,  Masahiro Okabe

发明人： Mari Hodate ,  Norihisa Matsumoto ,  Kohji Ohgata ,  Tamotsu Wada ,  Ken-iti Yanai ,  Ken-ichi Oki ,  Yasuyoshi Mishima ,  Michiko Takei ,  Tatsuya Kakehi ,  Masahiro Okabe

IPC分类号： G02F1/1362 ,  H01L21/265 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8232

CPC分类号： H01L29/66757 ,  G02F1/13454 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78621 ,  Y10S438/948

摘要： A method of manufacturing a semiconductor device according to the present invention includes a process of introducing impurities into a semiconductor layer with a gate electrode and a resist film as a mask after a resist film is formed on the top and the side of the gate electrode by soaking the gate electrode on a semiconductor layer in an electrolyte containing resist and applying voltage to the gate electrode.

摘要翻译： 根据本发明的制造半导体器件的方法包括在栅电极的顶部和侧面上形成抗蚀剂膜之后，将杂质引入到具有栅电极和抗蚀剂膜作为掩模的半导体层中的工艺， 将栅极电极浸入含有抗蚀剂的电解质的半导体层上并向栅电极施加电压。

公开(公告)号：US06677222B1

公开(公告)日：2004-01-13

申请号：US09637276

申请日：2000-08-11

申请人： Yasuyoshi Mishima ,  Katsuyuki Suga ,  Michiko Takei ,  Akito Hara

发明人： Yasuyoshi Mishima ,  Katsuyuki Suga ,  Michiko Takei ,  Akito Hara

IPC分类号： H01L2120

CPC分类号： H01L21/02675 ,  H01L21/2022 ,  H01L21/2026

摘要： A first layer made of polysilicon is formed on the surface of an underlying substrate. The surface of the first layer is exposed to an environment which etches silicon oxide. If the surface of the first layer is covered with a silicon oxide film, the silicon oxide film is removed. An energy is supplied to the first layer, the energy allowing silicon crystal to re-grow. Solid phase growth of silicon occurs in the first layer to planarize the surface thereof. A polysilicon film having small root mean square of roughness can be formed.

摘要翻译： 在下面的衬底的表面上形成由多晶硅制成的第一层。 第一层的表面暴露于蚀刻氧化硅的环境中。 如果第一层的表面被氧化硅膜覆盖，则去除氧化硅膜。 能量被供应到第一层，能量允许硅晶体再生长。 在第一层中发生硅的固相生长以平坦化其表面。 可以形成具有小的粗糙度均方根的多晶硅膜。

公开(公告)号：US06884666B2

公开(公告)日：2005-04-26

申请号：US10624074

申请日：2003-07-21

申请人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

发明人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

IPC分类号： G02F1/136 ,  G02F1/1345 ,  G02F1/1368 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645

摘要： A current path pattern of semiconductor material is formed on the insulating principal surface of a substrate. A gate pattern three-dimensionally crosses the current path pattern in first and second cross areas. A channel region of the current path pattern is defined in an area superposed upon by the gate pattern. A gate insulating film is disposed between the current path pattern and gate pattern. The current path pattern has a lightly doped drain structure on both sides of the channel region in the first cross area, and is not provided with the lightly doped drain structure in regions in contact with the channel region in the second cross area. TFTs are provided having a small off-current and being not necessary for high precision position alignment during manufacture processes even if a gate length is short.

摘要翻译： 半导体材料的电流路径图案形成在基板的绝缘主表面上。 栅极图案在第一和第二交叉区域中三维地穿过当前路径图案。 当前路径图案的通道区域被限定在由栅极图案叠加的区域中。 栅极绝缘膜设置在电流路径图案和栅极图案之间。 电流路径图案在第一交叉区域中的沟道区域的两侧上具有轻掺杂的漏极结构，并且在与第二十字区域中的沟道区域接触的区域中不设置轻掺杂漏极结构。 提供具有小的截止电流的TFT，并且即使栅极长度短，也不需要在制造过程中的高精度位置对准。

公开(公告)号：US06628349B1

公开(公告)日：2003-09-30

申请号：US09651876

申请日：2000-08-30

申请人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

发明人： Michiko Takei ,  Yasuyoshi Mishima ,  Mitsuru Chida ,  Kohta Yoshikawa

IPC分类号： G02F1136

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645

摘要： A liquid crystal display substrate including gate and drain bus lines that are electrically insulated from each other at cross areas, pixel electrodes between the cross areas, and first thin film transistors connecting corresponding drain bus lines and pixel electrodes. Each first thin film transistor includes a channel region where current flows in a first direction, and first and second impurity doped regions of, respectively, first and second impurity concentrations. The first and second doped regions sandwich the channel region. The second impurity concentration is higher than the first. Also, a second thin film transistor is formed in the peripheral circuit area, and includes a channel region where current flows in a second direction that is perpendicular to the first direction. Third impurity doped regions, disposed on both sides of the channel region, have a third impurity concentration.

摘要翻译： 一种液晶显示基板，包括在交叉区域彼此电绝缘的栅极和漏极总线，以及交叉区域之间的像素电极和连接相应的漏极总线和像素电极的第一薄膜晶体管。 每个第一薄膜晶体管包括电流沿第一方向流动的沟道区，以及分别为第一和第二杂质浓度的第一和第二杂质掺杂区。 第一和第二掺杂区夹着沟道区。 第二杂质浓度高于第一杂质浓度。 此外，第二薄膜晶体管形成在外围电路区域中，并且包括电流沿与第一方向垂直的第二方向流动的沟道区域。 设置在沟道区两侧的第三杂质掺杂区具有第三杂质浓度。

公开(公告)号：US5515072A

公开(公告)日：1996-05-07

申请号：US455726

申请日：1995-05-31

申请人： Kenichi Yanai ,  Kenichi Oki ,  Tetsuya Hamada ,  Kazuhiro Takahara ,  Yasuyoshi Mishima ,  Tsutomu Tanaka

发明人： Kenichi Yanai ,  Kenichi Oki ,  Tetsuya Hamada ,  Kazuhiro Takahara ,  Yasuyoshi Mishima ,  Tsutomu Tanaka

IPC分类号： G02F1/1362 ,  G09G3/36

CPC分类号： G09G3/3659 ,  G09G3/3648 ,  G02F2001/136245 ,  G02F2201/122 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2310/0224 ,  G09G2310/0281 ,  G09G2320/0204 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2320/0247 ,  G09G2330/08 ,  G09G3/3614

摘要： In an active matrix-type display device where scan bus lines (S.sub.i) and data bus lines (D.sub.j) are formed on different substrates, two kinds of scan bus lines (SP.sub.i, SN.sub.i) are provided. A first switching element (TFTN.sub.ij) is connected between a reference voltage supply line (V.sub.R) and a display electrode (E.sub.ij), and is controlled by a first scan bus line (SN.sub.i), and a second switching element (TFTP.sub.ij) is connected between the reference voltage supply bus line (V.sub.R) and the display electrode, and is controlled by a second scan bus line (SP.sub.i). The first switching element (TFTN.sub.ij) is turned ON by a positive or negative potential at the first scan bus line.

公开(公告)号：US07947547B2

公开(公告)日：2011-05-24

申请号：US12137807

申请日：2008-06-12

申请人： Teruo Kurahashi ,  Manabu Sakamoto ,  Yasuyoshi Mishima

发明人： Teruo Kurahashi ,  Manabu Sakamoto ,  Yasuyoshi Mishima

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment. By controlling the nitrogen content of each layer and the amount of nitrogen that diffuses, a low-resistance metal gate electrode having a predetermined work function can be formed in each of the nMOS transistor formation region and the pMOS transistor formation region.

摘要翻译： 可以制造具有各自具有适当功函数的具有低电阻金属栅电极的CMOS晶体管的半导体器件制造方法。 形成其中nMOS晶体管形成区域中的氮浓度与pMOS晶体管形成区域中的氮浓度不同的HfN层。 在HfN层上形成MoN层，进行热处理。 氮从MoN层扩散到HfN层，其中氮浓度低，并且通过HfN层根据氮浓度设定功函数，氮浓度取决于热处理前的HfN层的氮含量和氮的量 扩散到HfN层。 另一方面，氮几乎从MoN层扩散到原来具有一定氮含量的HfN层中，并且通过HfN层根据HfN层中的氮浓度在热处理之前设定功函数。 通过控制各层的氮含量和扩散的氮的量，可以在nMOS晶体管形成区域和pMOS晶体管形成区域中的每一个中形成具有预定功函数的低电阻金属栅电极。

公开(公告)号：US20100044799A1

公开(公告)日：2010-02-25

申请号：US12541556

申请日：2009-08-14

申请人： Teruo Kurahashi ,  Yasuyoshi Mishima ,  Yukie Sakita

发明人： Teruo Kurahashi ,  Yasuyoshi Mishima ,  Yukie Sakita

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66545

摘要： A method for manufacturing a P-type MOS transistor includes forming a gate insulating film on the substrate, forming a gate electrode from amorphous silicon containing no impurities on the gate insulating film, performing a heat treatment for controlling the film characteristics of the amorphous silicon, depositing a nickel (Ni) layer on the gate electrode, and forming nickel silicides from the gate electrode and the nickel (Ni).

摘要翻译： 一种P型MOS晶体管的制造方法，其特征在于，在所述基板上形成栅极绝缘膜，在所述栅极绝缘膜上形成不含有杂质的非晶硅的栅电极，进行用于控制所述非晶硅的膜特性的热处理， 在栅电极上沉积镍（Ni）层，并从栅电极和镍（Ni）形成镍硅化物。

公开(公告)号：US20090057739A1

公开(公告)日：2009-03-05

申请号：US12230448

申请日：2008-08-28

申请人： Hiroshi Iwai ,  Takeo Hattori ,  Kazuo Tsutsui ,  Kuniyuki Kakushima ,  Parhat Ahmet ,  Jaeyeol Song ,  Masaki Yoshimaru ,  Yasuyoshi Mishima ,  Tomonori Aoyama ,  Hiroshi Oji ,  Yoshitake Kato

发明人： Hiroshi Iwai ,  Takeo Hattori ,  Kazuo Tsutsui ,  Kuniyuki Kakushima ,  Parhat Ahmet ,  Jaeyeol Song ,  Masaki Yoshimaru ,  Yasuyoshi Mishima ,  Tomonori Aoyama ,  Hiroshi Oji ,  Yoshitake Kato

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/517 ,  C23C14/021 ,  C23C14/024 ,  C23C14/08 ,  C23C14/18 ,  C23C14/30 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/31604 ,  H01L29/78

摘要： The Ge channel device comprises: a Ge channel layer (2); a Si-containing interface layer (4) formed on the Ge channel layer (2); a La2O3 layer (6) formed on the interface layer (4); and an electrically conductive layer (8) formed on the La2O3 layer (6). In this device, the Si-containing interface layer (4) functions to suppress the diffusion of Ge atoms into the La2O3 layer (6) and thereby prevents the formation of Ge oxide in the La2O3 layer (6); accordingly, a Ge channel device whose C-V characteristic exhibits only a small hysteresis can be achieved.

摘要翻译： Ge沟道器件包括：Ge沟道层（2）; 形成在所述Ge沟道层（2）上的含Si界面层（4）; 在所述界面层（4）上形成的La 2 O 3层（6）; 和形成在La 2 O 3层（6）上的导电层（8）。 在该器件中，含Si界面层（4）用于抑制Ge原子扩散到La2O3层（6）中，从而防止La2O3层（6）中Ge氧化物的形成; 因此，可以实现其C-V特性仅具有小滞后的Ge通道器件。

公开(公告)号：US07399662B2

公开(公告)日：2008-07-15

申请号：US11246812

申请日：2005-10-07

申请人： Ken-ichi Yanai ,  Yoshio Nagahiro ,  Kazushige Hotta ,  Koji Ohgata ,  Yasuyoshi Mishima ,  Nobuo Sasaki

发明人： Ken-ichi Yanai ,  Yoshio Nagahiro ,  Kazushige Hotta ,  Koji Ohgata ,  Yasuyoshi Mishima ,  Nobuo Sasaki

IPC分类号： H01L21/00

CPC分类号： H01L27/12 ,  H01L27/1237 ,  H01L27/1248 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624

摘要： A method of making a thin film transistor device, including forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and high-voltage driven thin film transistor formation regions. The method also includes forming a first insulating film on the first and second semiconductor films, and forming a first gate electrode on the first insulating film in the low-voltage driven thin film transistor formation region. Additionally, a second insulating film is formed on the entire surface of the resultant structure above the substrate, and a second gate electrode is formed on the second insulating film in the high-voltage driven thin film transistor formation region. The method also includes etching the first and second insulating films, thus forming first and second gate insulating films below, respectively, the first and second gate electrodes, with the second gate insulating film being wider than the second gate electrode.

摘要翻译： 一种制造薄膜晶体管器件的方法，包括形成和构图半导体膜，以分别形成低压驱动和高电压驱动的薄膜晶体管形成区域中的第一和第二半导体膜。 该方法还包括在第一和第二半导体膜上形成第一绝缘膜，以及在低电压驱动薄膜晶体管形成区域中的第一绝缘膜上形成第一栅电极。 此外，在基板上方的所得结构的整个表面上形成第二绝缘膜，并且在高电压驱动薄膜晶体管形成区域中的第二绝缘膜上形成第二栅电极。 该方法还包括蚀刻第一和第二绝缘膜，从而分别在第一和第二栅极电极之下形成第一和第二栅极绝缘膜，其中第二栅极绝缘膜比第二栅极电极宽。

公开(公告)号：US20070059875A1

公开(公告)日：2007-03-15

申请号：US11585804

申请日：2006-10-25

申请人： Yasuyoshi Mishima

发明人： Yasuyoshi Mishima

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/268 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78684 ,  H01L29/78687

摘要： A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed in the first semiconductor layer; and a gate layered body formed of a gate insulating film and a gate electrode on the first semiconductor layer is disclosed. The method includes the steps of (a) forming a second semiconductor layer by epitaxial growth on the first semiconductor layer; (b) heating the second semiconductor layer; and (c) removing the second semiconductor layer. The second semiconductor layer is different in lattice constant in an in-plane direction from the first semiconductor layer. Step (b) induces the strain in the first semiconductor layer by exposing the surface of the second semiconductor layer to energy lines.

摘要翻译： 一种制造包括衬底的半导体器件的方法; 在其上形成绝缘膜; 第一半导体层，其在与所述基板的表面平行的方向上产生应变，所述第一半导体层位于所述绝缘膜上; 形成在所述第一半导体层中的源极区域和漏极区域; 并且公开了在第一半导体层上由栅极绝缘膜和栅电极形成的栅极层叠体。 该方法包括以下步骤：（a）通过外延生长在第一半导体层上形成第二半导体层; （b）加热第二半导体层; 和（c）去除第二半导体层。 第二半导体层在与第一半导体层的面内方向上的晶格常数不同。 步骤（b）通过将第二半导体层的表面暴露于能量线来引起第一半导体层中的应变。