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公开(公告)号：US20060258045A1
公开(公告)日：2006-11-16
申请号：US11412127
申请日：2006-04-27
申请人： Masahiko Ishiguri , Hirohisa Matsuki , Hiroyuki Yoda , Tadahiro Okamoto , Masamitsu Ikumo , Shuichi Chiba
发明人： Masahiko Ishiguri , Hirohisa Matsuki , Hiroyuki Yoda , Tadahiro Okamoto , Masamitsu Ikumo , Shuichi Chiba
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1147 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2924/0105 , H01L2224/13099
摘要： A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X½)≦X2≦(3*X¼) and (X½)≦X3≦(3*X¼).
摘要翻译： 半导体器件包括半导体衬底和以间距X1布置的突出电极阵列。 每个突出电极具有高度X3，并且形成在直径为X2的阻挡金属基底上，耦合到布置在半导体衬底上的电极，以满足关系式（X 1/2）<= X2 <=（3 *X¼）和（ X½）<= X3 <=（3 *X¼）。
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公开(公告)号：US20050140004A1
公开(公告)日：2005-06-30
申请号：US10995081
申请日：2004-11-23
申请人： Masahiko Ishiguri , Hirohisa Matsuki , Hiroyuki Yoda , Tadahiro Okamoto , Masamitsu Ikumo , Shuichi Chiba
发明人： Masahiko Ishiguri , Hirohisa Matsuki , Hiroyuki Yoda , Tadahiro Okamoto , Masamitsu Ikumo , Shuichi Chiba
IPC分类号： H01L21/60 , H01L21/28 , H01L21/768 , H01L23/02 , H01L23/48 , H01L23/485 , H01L23/52
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1147 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2924/0105 , H01L2224/13099
摘要： A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)≦X2≦(3*X1/4) and (X1/2)≦X3≦(3*X1/4).
摘要翻译： 半导体器件包括半导体衬底和以间距X 1布置的突出电极阵列。 每个突出电极具有高度X 3，并且形成在与布置在半导体衬底上的电极耦合的直径为X 2的阻挡金属基底上，以满足关系（X 1/2）<= X 2 <=（ 3 * X 1/4）和（X 1/2）<= X 3 <=（3 * X 1/4）。
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公开(公告)号：US07064436B2
公开(公告)日：2006-06-20
申请号：US10995081
申请日：2004-11-23
申请人： Masahiko Ishiguri , Hirohisa Matsuki , Hiroyuki Yoda , Tadahiro Okamoto , Masamitsu Ikumo , Shuichi Chiba
发明人： Masahiko Ishiguri , Hirohisa Matsuki , Hiroyuki Yoda , Tadahiro Okamoto , Masamitsu Ikumo , Shuichi Chiba
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1147 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2924/0105 , H01L2224/13099
摘要： A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)≦X2≦(3*X1/4) and (X1/2)≦X3≦(3*X1/4).
摘要翻译： 半导体器件包括半导体衬底和以间距X 1布置的突出电极阵列。 每个突出电极具有高度X 3，并且形成在与布置在半导体衬底上的电极耦合的直径为X 2的阻挡金属基底上，以满足关系（X 1/2）<= X 2 <=（ 3 * X 1/4）和（X 1/2）<= X 3 <=（3 * X 1/4）。
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公开(公告)号：US06734042B2
公开(公告)日：2004-05-11
申请号：US10207815
申请日：2002-07-31
申请人： Masamitsu Ikumo , Hirohisa Matsuki
发明人： Masamitsu Ikumo , Hirohisa Matsuki
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/45144 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2924/00
摘要： A group of wires that bonds the first semiconductor chip and the second semiconductor chip together and extends on the first semiconductor chip is formed of a single plated film through plating in one continuous process. The second semiconductor chip is then bonded onto the first semiconductor chip to complete a semiconductor package.
摘要翻译： 将第一半导体芯片和第二半导体芯片结合在一起并在第一半导体芯片上延伸的一组电线通过一个连续工艺中的电镀由单个镀膜形成。 然后将第二半导体芯片接合到第一半导体芯片上以完成半导体封装。
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公开(公告)号：US20050224970A1
公开(公告)日：2005-10-13
申请号：US10924206
申请日：2004-08-24
申请人： Hirohisa Matsuki , Masamitsu Ikumo
发明人： Hirohisa Matsuki , Masamitsu Ikumo
IPC分类号： H01L27/04 , H01L21/60 , H01L21/66 , H01L21/822 , H01L23/48 , H01L23/498 , H01L23/52 , H01L23/58
CPC分类号： H01L22/32 , H01L23/49855 , H01L2224/02166 , H01L2224/0401 , H01L2224/1147 , Y10S257/922
摘要： A semiconductor device has antenna pads and a testing pad formed on the substrate. An insulating resin layer containing a filler covers the testing pad, and bumps are provided on the antenna pads. Specific data in the semiconductor device are inhibited from being read out or rewritten, by the provision of the insulating resin layer containing a filler.
摘要翻译： 半导体器件具有形成在衬底上的天线焊盘和测试焊盘。 包含填充物的绝缘树脂层覆盖测试垫，并且在天线焊盘上设置凸块。 通过设置含有填料的绝缘树脂层，可以抑制半导体器件中的具体数据被读出或重写。
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公开(公告)号：US06836025B2
公开(公告)日：2004-12-28
申请号：US10448444
申请日：2003-05-30
申请人： Tetsuya Fujisawa , Hirohisa Matsuki , Osamu Igawa , Yoshitaka Aiba , Masamitsu Ikumo , Mitsutaka Sato
发明人： Tetsuya Fujisawa , Hirohisa Matsuki , Osamu Igawa , Yoshitaka Aiba , Masamitsu Ikumo , Mitsutaka Sato
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/49822 , H01L23/5383 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/48 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2223/54426 , H01L2223/5446 , H01L2224/04042 , H01L2224/04105 , H01L2224/05599 , H01L2224/12105 , H01L2224/16145 , H01L2224/24137 , H01L2224/24145 , H01L2224/24155 , H01L2224/24195 , H01L2224/24226 , H01L2224/24265 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/4847 , H01L2224/48471 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/83856 , H01L2224/85399 , H01L2224/92 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12044 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2924/19107 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor device circuit formation surfaces of each of a plurality of semiconductor chips can be easily located at even level when the semiconductor chips are arranged side by side so that a process of forming rearrangement wiring is simplified. The semiconductor chips are mounted on a substrate via an adhesive layer in a two-dimensional arrangement. A resin layer is formed on the substrate and located around the semiconductor elements. The resin layer has the same thickness as a thickness of the semiconductor elements. An organic insulating layer is formed over a surface of the resin layer and circuit formation surfaces of the semiconductor elements. A rearrangement wiring layer is formed on the organic insulating layer and electrodes of the semiconductor chips. External connection terminals are electrically connected to the circuit formation surfaces of the semiconductor elements through wiring in the rearrangement wiring layer.
摘要翻译： 在半导体器件中，当半导体芯片并排布置时，多个半导体芯片中的每一个的形成表面可以容易地位于均匀的水平，从而简化了布置布线的处理。 半导体芯片通过二维布置的粘合剂层安装在基板上。 树脂层形成在基板上并位于半导体元件周围。 树脂层的厚度与半导体元件的厚度相同。 在树脂层的表面和半导体元件的电路形成表面上形成有机绝缘层。 在有机绝缘层和半导体芯片的电极上形成重排布线层。 外部连接端子通过布线布线层中的布线电连接到半导体元件的电路形成表面。
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7.发明授权公开(公告)号：US07233076B2
公开(公告)日：2007-06-19
申请号：US10924206
申请日：2004-08-24
申请人： Hirohisa Matsuki , Masamitsu Ikumo
发明人： Hirohisa Matsuki , Masamitsu Ikumo
IPC分类号： H01L23/29
CPC分类号： H01L22/32 , H01L23/49855 , H01L2224/02166 , H01L2224/0401 , H01L2224/1147 , Y10S257/922
摘要： A semiconductor device has antenna pads and a testing pad formed on the substrate. An insulating resin layer containing a filler covers the testing pad, and bumps are provided on the antenna pads. Specific data in the semiconductor device are inhibited from being read out or rewritten, by the provision of the insulating resin layer containing a filler.
摘要翻译： 半导体器件具有形成在衬底上的天线焊盘和测试焊盘。 包含填充物的绝缘树脂层覆盖测试垫，并且在天线焊盘上设置凸块。 通过设置含有填料的绝缘树脂层，可以抑制半导体器件中的具体数据被读出或重写。
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公开(公告)号：US06548898B2
公开(公告)日：2003-04-15
申请号：US09895330
申请日：2001-07-02
申请人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
发明人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
IPC分类号： H01L2352
CPC分类号： H01L24/05 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L2224/02126 , H01L2224/03462 , H01L2224/0401 , H01L2224/04026 , H01L2224/05 , H01L2224/05554 , H01L2224/05568 , H01L2224/05571 , H01L2224/05572 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/1358 , H01L2224/16 , H01L2224/274 , H01L2224/814 , H01L2924/0001 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/13091 , H01L2924/15787 , H01L2924/351 , H05K3/244 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
摘要翻译： 其中磷镍层，含有比该磷 - 镍层高的磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是 在电极上依次形成。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。
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公开(公告)号：US20050074971A1
公开(公告)日：2005-04-07
申请号：US10778152
申请日：2004-02-17
申请人： Masamitsu Ikumo , Hirohisa Matsuki
发明人： Masamitsu Ikumo , Hirohisa Matsuki
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07 , H01L21/302 , H01L21/461
CPC分类号： H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/45144 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2924/00
摘要： A group of wires that bonds the first semiconductor chip and the second semiconductor chip together and extends on the first semiconductor chip is formed of a single plated film through plating in one continuous process. The second semiconductor chip is then bonded onto the first semiconductor chip to complete a semiconductor package.
摘要翻译： 将第一半导体芯片和第二半导体芯片结合在一起并在第一半导体芯片上延伸的一组电线通过一个连续工艺中的电镀由单个镀膜形成。 然后将第二半导体芯片接合到第一半导体芯片上以完成半导体封装。
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公开(公告)号：US06784543B2
公开(公告)日：2004-08-31
申请号：US10374965
申请日：2003-02-28
申请人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
发明人： Hirohisa Matsuki , Yutaka Makino , Masamitsu Ikumo , Mitsutaka Sato , Tetsuya Fujisawa , Yoshitaka Aiba
IPC分类号： H01L2352
CPC分类号： H01L24/05 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/94 , H01L24/96 , H01L2224/02126 , H01L2224/03462 , H01L2224/0401 , H01L2224/04026 , H01L2224/05 , H01L2224/05554 , H01L2224/05568 , H01L2224/05571 , H01L2224/05572 , H01L2224/13006 , H01L2224/13021 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/1358 , H01L2224/16 , H01L2224/274 , H01L2224/814 , H01L2924/0001 , H01L2924/00011 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/13091 , H01L2924/15787 , H01L2924/351 , H05K3/244 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A structure in which a phosphorus-nickel layer, a rich phosphorus nickel layer that contains phosphorus or boron higher than this phosphorus-nickel layer, a nickel-tin ally layer, a tin-rich tin alloy layer, and a tin alloy solder layer are formed in sequence on an electrode. Accordingly, adhesiveness between a metal pattern used as the electrode, the wiring, or the pad and the solder can be improved.
摘要翻译： 其中磷镍层，含有比该磷 - 镍层高的磷或硼的富磷镍层，镍锡合金层，富锡锡合金层和锡合金焊料层的结构是 在电极上依次形成。 因此，可以提高用作电极的金属图案，布线或焊盘和焊料之间的粘合性。
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